64-bit Tick Count and Wait Function Reference Example for LabVIEW FPGA

[ExamplePrograms]

Overview

The Tick Count and Wait functions in LabVIEW FPGA provide resolution of 8-bit, 16-bit and 32-bit. In some advanced applications, timing operations using 64-bit value ranges is necessary. This reference example provides implementations of a 64-bit Tick Count and 64-bit Wait function.

Tick Count

The standard Tick Count function in LabVIEW FPGA can represent time periods with tick count accuracy of up to 2^32 clock cycles. Using the standard 40 MHz FPGA clock this represents ~107 seconds. For applications that need to store or measure longer time periods with tick count accuracy, a larger range tick count function is required. This reference example provides a tick count function with a 64-bit count value. This provides a maximum time range of 2^64 clock cycles or ~14623 years at 40 MHz.

The 64-bit tick count is implemented as a clock engine which runs in parallel with the rest of the LabVIEW FPGA VI. The Tick Count Engine updates a global tick count variable which can be read in any other part of the FPGA application.  The Tick Count Global also contains a Stop value which can be used to shutdown the Tick Count Engine if desired.

Figure 1: Example using the 64-bit Tick Count engine and global variable.

To use the 64-bit tick count, place the Tick Count (U64) Engine VI in your main VI so that it is called immediately when the main VI is started. Do not place the engine inside of a loop or other programming structure so that other code has data dependency on the Tick Count engine. The engine VI does not return until it is stopped and will block any other code waiting for it to complete.

To read the current 64-bit tick count value, place the Tick Count (U64) global variable anywhere in your VI or any subVI of the main FPGA VI.

Wait

The 64-bit Wait function is implemented as a Single Cycle Timed Loop that decrements a shift register initialized with the Wait Count value. The Wait function is completed when the shift register reaches zero.