Adjustable Backplane Clock With the 5406/02

Publish Date: Nov 21, 2013 | 0 Ratings | 0.00 out of 5 | Print | Submit your review


This examples demonstrates how to generate an adjustable clock with the 5406 or the 5402 and route it to any of the TRIG lines of the back plane.


Our signal sources 5406 and 5402 (standard function generators) have the feature of generating very high resolution periodical signal by using a technique called DDS (direct digital synthesis). Using this ability you can generate a clock and route to the back plane allowing you to adjust the clock. 

Setting it Up:

To use this example you will have to connect CH0 to the PFI0 line and make sure you are selecting the correct source and destination terminals on the: "Connect".



After you have this code up and running you will be able to use as your sample clock or reference clock for other cards connected to the chassis. The ability to use a TRIG line as the source for the sample clock or the reference clock is device specific and should be checked on the specifications. 

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