Multiply Accumulate (MAC) optimized for DSP48E slice using HDL node

Publish Date: Apr 26, 2012 | 7 Ratings | 3.43 out of 5 | Print | Submit your review

Overview

A Multiply Accumulate (MAC) operation is a common type of operation in FPGA that can be carried out in normal logic or optimized with the Virtex-5 FPGAs using a special slice called the DSP48E.

To specifically target a DSP48E slice, low-level HDL code needs to be used to show the compiler how to use this slice.

This example contains an HDL node setup to use the DSP48E slice. Furthermore, there is a VI for testing that uses a simulation VI to run the HDL node in emulation mode without a target or the need to compile.

1. Multiply Accumulate (MAC) optimized for DSP48E slice using HDL node

The Zip file, DSP48E_HDL_MAC.zip, contains a project and several VIs

Testbench.VI:  This VI will allow you to test the MAC functionality in emulation mode using the simulation VI.

MAC_SCTL (VI Debugging VI).VI:  This is the simulation VI that allows you to run the HDL node in emulation mode.  It is important to note, the VI is setup with feedback nodes for pipelined operation. 

 DSP48E.VI: This VI contains the actual HDL node and code designed to utilize the DSP48E slice.  This VI is all that is needed to run the HDL node on a Virtex-5 FPGA target.  The other VIs are for emulation.

Back to Top

2. Additional Resources 

Advantages of Xilinx Virtex-5 FPGAs

IPNet - LabVIEW FPGA Functions and Example IP

National Instruments R Series Intelligent Data Acquisition Devices

National Instruments LabVIEW FPGA Module

 

Back to Top

Bookmark & Share


Downloads

Attachments:

DSP48E_HDL_MAC

Requirements


Ratings

Rate this document

Answered Your Question?
Yes No

Submit