Overview
This is an optimized example for streaming data from FPGA to cRIO to Windows.
Note: This example is optimized for throughput and CPU Usage. Therefore, some determinism is lost. The cases where this is true are documented below.
This example has been optimized for streaming data from FPGA to cRIO to Windows. Specifically, a cRIO VxWorks target (NI 9012, NI 9014, NI 9074, etc.) was used as they have more powerful CPUs then their Pharlap counterparts (NI 9002, NI 9004). This example was able to do 24 channels @ 50 kS with a CPU usage of around 92%. For continuous logging over long periods of time, you should consider lowering the CPU usage by using fewer channels or by using a lower sample rate. This is to allow for some CPU headroom in case of CPU spikes, etc.
There are three parts to this example. A FPGA VI, Real-Time (RT) VI and Windows VI.
The FPGA VI is basically acquiring data, passing it to a Target to Host DMA FIFO, and firing a IRQ after a pre-determined number of loop iterations. This IRQ is signaling the Host that the data is ready. The IRQ allows the Host CPU to process other parts of the Host code until the IRQ is fired. However, IRQs generally takes longer to process by the Host and is therefore more efficient but less deterministic. The FPGA VI does not wait for the IRQ to be acknowledged. This guarantees that the analog input sampling rate stays constant.
The RT VI consists of reading from the FPGA DMA FIFO, passing data to a communication loop, and sending the data to a Windows Host. The data is passed to the communication loop via a RT FIFO. This RT FIFO is set to blocking on reads, which acts similar to the IRQs described above. It basically is more CPU efficient but sacrifices a little determinism. The data is sent to Windows via TCP. This is because this is the most efficient method of transferring data in a loss-less format over a network. Priorities in the RT VI are set so that the FPGA DMA Read is the highest priority, followed by the TCP Communication Loop and then everything else is in the normal priority. This is to ensure that data gets off of the FPGA and to Windows before other threads execute.
The Windows VI is simply reading the data from the cRIO via TCP and sends it to a second processing loop via Queues. The Queues give a bit of a software buffer that will help guard against falling behind temporarily in analysis, etc.
Currently, you will need to add your IO to the FPGA VI and re-compile the FPGA VI. If you change FPGA Targets, you will also need to re-compile. If you want your FPGA IO to be calibrated, it is easiest to do so through the FPGA IO Node, which is a new feature in the NI-RIO Driver version 2.4.0. Otherwise, you will have to program much more FPGA, RT, and Windows code to get the calibrated data. See KnowledgeBase: Using Fixed-Point Data with CompactRIO and LabVIEW FPGA for more information on using Fixed-Point in LabVIEW FPGA and cRIO.
