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LabVIEW FPGA Module

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Description

Overview

HDLC (High-Level Data Link Control) is a serial digital protocol that can be used to communicate between different nodes on a network. Many of today's commonly-used communication standards are built on the HDLC specification, which describes how to serially transmit frames of data with control registers and error checking.

This is an example of how to implement an HDLC interface with the LabVIEW FPGA Module and R Series Intelligent DAQ hardware.

HDLC Implementation Example for LabVIEW FPGA

HDLC_Host.vi is designed as a driver VI that can be called from a test console or other test executive application. It uses a state machine architecture to initialize the FPGA hardware, send commands, receive data and then close the connection.

HDLC_FPGA.vi can operate in on-demand or continuously transmit mode. Each bit being transmitted can be synchronized to an internal or external clock. Responses are received continuously and can be dumped to the Host via DMA transfer or analyzed on the FPGA.

There are three main loops in the FPGA application.

HDLC transmission loop
Data receive loop
Clock generation loop

This LabVIEW FPGA example code was developed by PLF Consulting.