HDLC Implementation in LabVIEW FPGA

Publish Date: Jan 14, 2010 | 6 Ratings | 3.33 out of 5 | Print | 2 Customer Reviews | Submit your review

Overview

HDLC (High-Level Data Link Control) is a serial digital protocol that can be used to communicate between different nodes on a network. Many of today's commonly-used communication standards are built on the HDLC specification, which describes how to serially transmit frames of data with control registers and error checking.

This is an example of how to implement an HDLC interface with the LabVIEW FPGA Module and R Series Intelligent DAQ hardware.

1. HDLC Implementation Example for LabVIEW FPGA

HDLC_Host.vi is designed as a driver VI that can be called from a test console or other test executive application.  It uses a state machine architecture to initialize the FPGA hardware, send commands, receive data and then close the connection.

HDLC_FPGA.vi can operate in on-demand or continuously transmit mode.  Each bit being transmitted can be synchronized to an internal or external clock.  Responses are received continuously and can be dumped to the Host via DMA transfer or analyzed on the FPGA.

There are three main loops in the FPGA application.

  • HDLC transmission loop
  • Data receive loop
  • Clock generation loop

This LabVIEW FPGA example code was developed by PLF Consulting.

 

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2. Additional Resources

National Instruments LabVIEW FPGA Module

R Series Intelligent DAQ

Developing Digital Communication Interfaces with LabVIEW FPGA 

Implementing a Custom Serial Protocol with Intelligent DAQ

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Customer Reviews
2 Reviews | Submit your review

Tried to open DMA_HDLC_DynamicRead.vi  - Oct 2, 2014

Can't find: C:\test\VIs\FPGA_Tango\FPGA Bitfiles\Tango.lvproj_FPGA Target_FPGA_Tango(T1_rev4~96.lvbit and HDLC\FPGA\Controls\FPGA_VI_Reference_(PCI).ctl

FPGA_HDLC.vi   - May 17, 2010

- the labels of the two bit arrays "7E_Patter..." at the left are irritating. What is the intention of the first four bytes? - the CMD data (16 bit) are inserted in the address byte and data hi -byte. The comment ("FF: Address") does not fit. - the receive loop does not filter the stuffing bits - the receive loop works with multiples of 32 bit only.

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HDLC with LabVIEW FPGA

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