CompactRIO Simultaneous AI and AO Streaming

Publish Date: Jan 29, 2008 | 4 Ratings | 2.75 out of 5 | Print | 1 Customer Review | Submit your review


This example shows how to simultaneously stream AI and AO data between the RT controller and FPGA on a 9002/4 controller using a NI 9215 module for analog input and NI 9263 module for analog output. DMA is used for the analog input data stream from the FPGA to RT, while register I/O is used for the AO data streamed from RT to thye FPGA.

This example implements a continuous simultaneous analog input and analog output operation on the 9002/4 CompactRIO controller. Analog input is performed on a NI 9215 module, while analog output is performed on a NI 9263 module.

The analog input data is streamed from the FPGA to the RT controller using a DMA FIFO. The DMA FIFO is configured in the LV project. In the RT host VI, a DMA buffer is configured which receives the data from the DMA FIFO on the FPGA. Blocks of AI data read from the DMA buffer are displayed on a waveform graph.

The analog output data is streamed from RT to the FPGA using the FPGA host interface read/write node (register I/O). A FIFO is configured on the FPGA to buffer the AO data. The AO FIFO has 8192 elements. We will consider this to be a 8000 element buffer. From the RT host VI we write data in blocks to the AO FIFO on the FPGA. At the beginning of the VI we fill the AO FIFO once completely (8000 writes). Once the AO operation is started, the FPGA notifies the RT host whenever half the data in the buffer has been read and sent to the analog output. On this notification the RT host writes another half buffer worth of data to the AO FIFO (4000 writes).

In the RT host VI we simultaneously read data from the DMA buffer and check the AO operation for the next half buffer write operation. Neither of these operation can occupy the RT to FPGA interface for an extended period of time as otherwise the other operation would miss a necessary update. Therefore the timeout on the DMA read function is set to a small value (10 ms).

In this example the analog output waveform is defined in an array constant. This data could be read from a file or be generated using LabVIEW analysis VIs.

This example does not use cRIO calibration which would normally be part of an application. Therefore all data in this example is handled as binary values.

The cRIO-9002 and 9004 controllers do not support DMA data streaming from the RT host VI to the FPGA, which is the reason that the analog output stream is implemented using register I/O and a regular FIFO on the FPGA. The cRIO-9012 and 9014 controllers do support DMA streaming from the RT VI to the FPGA and the AO portion of the example could be changed to use DMA on these controllers.

Note: The example is updated for LabVIEW 8.5 and corrected some earlier issues in the code mistake.



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Customer Reviews
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  - Mar 25, 2007

There appears to be half an attempt to setup synchronisation handshaking between the RT and FPGA environments. "New AO Data" is set true by the RT so that the FPGA knows there is new data, but I cannot see where "New AO Data" is set false. Also, would you not get the same (and desired) result by just wiring "AO Data" directly to the "AO0" FPGA I/O and get rid of the "AO" FIFO and the "Write data from the Front Panel into the AO FIFO" loop, etc? Either I'm not seeing something or this example is seriously flawed (it works since it doesn't matter if you "overwrite" analog data, but means that the example cannot be used to transfer digital information).

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cRIO SIM AIO.lvproj


cRIO SIM AIO.lvproj



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