Simple SPI Communication with LabVIEW FPGA and the PXI-7831R

[ExamplePrograms]

This example generates and reads a 16-bit SPI packet with an active low ChipSelect signal. The two portions, input and output, of the example are normally used separately depending on which side of the communication you need. For this example we have implemented them both. The input code and output code use the same physical I/O lines which eliminates the need for any external wiring.

In this example the output code is the clock master and the input code is a clock slave. In some cases you might need an output which is a clock slave or input that is a clock master. More advanced SPI communication links can use bi-directional communication where the direction of data flow changes in the middle of one packet. You also can use two data lines, one for each direction.