IRIG-B Implementation in LabVIEW FPGA

Publish Date: Jan 14, 2010 | 2 Ratings | 4.00 out of 5 | Print | 2 Customer Reviews | Submit your review

This example contains an IRIG-B generator and decoder implemented in LabVIEW FPGA. The generator and decoder are implemented in two different LabVIEW FPGA VIs and are intended to run on different FPGA targets. The host VI downloads each FPGA personality to a different card and communicates with both to output an IRIG-B timing signal on one card and read it back in with the other card. The example is set up for a PXI-7811 and a PXI-7831R card, but the FPGA VIs and host VI can be easily updated for any of the RIO hardware targets.

The IRIG-B standard implemented in this example is the IRIG-B 000 variant.

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Customer Reviews
2 Reviews | Submit your review

  - Jun 20, 2012

I got it to work in LabVIEW 2011 with a PCI-7833R, wit a few modifications. I notice that the Year code is not implemented, and the day code was incorrectly implemented; I fixed that, and also amended it to run IRIG-A code without too much trouble. You should be able to get it to run in 2010 and future versions, if you figure out how to flip that bit on your particular FPGA card.

Update to LabVIEW 2010?  - Aug 8, 2010

Could this be updated for LabVIEW FPGA 2010? Since LabVIEW 7.x they integrated the FPGA module in the LabVIEW project so when this opens in LabVIEW 2010 it shows up with broken run arrows.

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Host IRIGB Communication with



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