Complete System Simulation of a 3-Phase Inverter Using NI Multisim and LabVIEW

Publish Date: Aug 27, 2014 | 12 Ratings | 2.92 out of 5 | Print | 1 Customer Review | Submit your review

Overview

With NI Multisim and NI LabVIEW software, you can implement desktop simulation of your entire analog and digital system before prototyping. This tutorial shows you how to use the Multisim and LabVIEW cosimulation feature to achieve closed-loop simulation of transistor-level power electronics as well as implement FPGA-based digital logic used for control.

It also examines the system simulation of a 3-phase inverter. Because the high-power analog circuit is developed in Multisim, it benefits from the new SPICE-based power electronics models featured in Multisim 12.0 such as the MOSFET switches and the nonideal RLCs. The digital logic blocks controlling the Multisim design are developed in LabVIEW.

A simultaneous point-by-point simulation that includes all of the system dynamics between the analog circuitry and the FPGA-based digital control system is performed. During this, processing resources are negotiated between both simulation engines in a variable time-step fashion. Accurate and complete desktop system simulation is now possible at an early stage of the design process.

Table of Contents

  1. System Requirements
  2. Introduction
  3. Design Flow
  4. Multisim Analog Circuitry
  5. LabVIEW Control Blocks
  6. Complete System Simulation 
  7. Hardware Implementation

1. System Requirements

  • Multisim 12.0
  • LabVIEW 2011
  • LabVIEW 2011 Control Design and Simulation Module
  • LabVIEW 2011 FPGA Module

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2. Introduction

What Is a Multisim and LabVIEW Complete System Simulation?

In traditional control logic design, engineers develop embedded code separate from the analog circuitry, but they eventually need to interact at a system level that is difficult to simulate simultaneously. This lack of simulation capabilities can result in embedded logic that does not properly account for analog circuitry (for example, the power design) and performs below expectations/specifications. This forces algorithm change and recompiles.

Multisim and LabVIEW enable codesign of an entire system, ensuring that algorithms and code simulated for the field-programmable gate array (FPGA) in LabVIEW are verified for performance with analog circuitry and can be directly implemented in hardware with minimal changes. This design approach is new in Multisim 12.0 and is called LabVIEW cosimulation.

Cosimulation allows a unique time-step negotiation between two simulation engines to create a closed-loop simulation of the complete system. The result is an evaluation of a design that includes all of the system dynamics between the analog and digital modules. Multisim, which is optimized for accurate analog and mixed-signal circuitry, includes a large set of predefined SPICE models from leading semiconductor manufacturers such as Analog Devices, NXP, ON Semiconductor, Texas Instruments, and others. The LabVIEW simulation engine is dedicated to the effective design and implementation of control logic through a graphical, dataflow representation. This engine provides high-level simulation optimized for embedded digital code for mechanical and power systems.

The result of this is a reduction in prototype iterations (up to three saved PCB turns) and accurate embedded code with fewer compiles (saving as much as four hours per compile).

 

Figure 1. Multisim 12.0 offers Multisim and LabVIEW cosimulation. 

Learn more about the basics of Multisim and LabVIEW cosimulation.

What Is a 3-Phase Inverter?

An inverter is an energy conversion circuit that receives a DC voltage input and converts it into AC. The most important parameters defining the quality of inverters are the power efficiency and the switching speed of the electronics involved in the circuit design. Common applications of high-power inverters are the integration of photovoltaic (PV) cells and wind turbines to power grids.

Learn more about NI green energy applications.

Find background information about inverters on Wikipedia

The inverter operation is based on using a DC input power as the bias stage of MOSFET switches for which the gates switching is controlled by high-frequency pulse-width modulated (PWM) signals. The MOSFET output stage is connected to a lowpass filter to attenuate the switching of high-frequency components. Closed-loop feedback is created by sampling the output of the inverter into the proportional integral derivative (PID) control logic and then to the PWM generator to ensure that the output matches the amplitude and locks to the phase of the system (in most of the cases the power grid).

Additional Resources

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3. Design Flow

The first step of this hardware design is the desktop simulation developed in Multisim and LabVIEW and highlighted in this tutorial. The different system blocks and the signal flow of the system are demonstrated in Figure 2.

 

Figure 2. System Block Diagram and Signal Flow

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4. Multisim Analog Circuitry

The analog circuit in Multisim consists of three stages:

  1. A 3-phase single-level inverter stage during which the DC input is sampled using the MOSFET switch based on the control PWM signals
  2. A filter stage to obtain a clean single frequency (60 or 50 Hz) signal
  3. A 3-phase load output stage during which the voltage and current are sampled using sensors in Multisim to provide input for the control blocks in LabVIEW

The schematic of this circuit is shown in Figure 3. Simply drag and drop to load it in your Multisim 12.0.

 

 

Figure 3. Developed 3-Phase Inverter Circuit in Multisim

 

The inputs to this Multisim design are the switch gate terminals (s1 to s6), and all of the other terminals connect to output signals either for monitoring or as part of the feedback loop.

 

The following table is exported from the Multisim LabVIEW terminals spreadsheet view and summarizes the connector modes.

 

LabVIEW terminal

Positive connection

Negative connection

Mode

Type

Input

 

 

 

 

s1

s1

0

Input

Voltage

s2

s2

0

Input

Voltage

s3

s3

0

Input

Voltage

s4

s4

0

Input

Voltage

s5

s5

0

Input

Voltage

s6

s6

0

Input

Voltage

Output

 

 

 

 

Va

Va

0

Output

Voltage

Vb

Vb

0

Output

Voltage

Vc

Vc

0

Output

Voltage

Va_l

Va_l

0

Output

Voltage

Vb_l

Vb_l

0

Output

Voltage

Vc_l

Vc_l

0

Output

Voltage

I_Lf1

I_Lf1

0

Output

Voltage

I_Rload1

I_Rload1

0

Output

Voltage

Vdc_link

Vdc_link

0

Output

Voltage

Vneutral

Vneutral

0

Output

Voltage

Unused

 

 

 

 

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5. LabVIEW Control Blocks

The LabVIEW control virtual instrument (VI) includes several blocks that are all placed in a control design and simulation loop running at 500 kHz. Each of these blocks performs one of the operations demonstrated in the design flow diagram.

The RMS Block

The RMS IP core control system acquires the load voltages and calculates the RMS value of the line-to-line voltages for 50 or 60 Hz. The RMS calculation is not valid for the first cycle of operation.

Figure 4. RMS VI and Block Diagram

 

The PID Control Block

The role of the PID control block is to regulate the amplitude of the 3-phase output line voltages based on the user-defined input value of the amplitude and the values of the PID control parameters Kp, Ki, and Kd.

Figure 5. PID Controller VI and Block Diagram

The Phase-Locked Loop (PLL) Block

The output filter shown in the analog design introduces phase delay to the output line voltages. The PLL block reads the phase information of the grid and locks the phase of the generated PWM signal and consequently the phase of the line voltages signal to be connected to the grid. The grid is represented by a virtual function block in the main block diagram of the application as shown later in this tutorial.

Figure 6. PLL Express VI

The Triangular Wave Generator and PWM operation

A 10 kHz triangular wave used for pulse-width modulation is generated by the FPGA IP core in Figure 7. The PWM operation occurs by comparing a generated sine wave based on the amplitude information received from the PID controller and the phase information received from the grid lines. The output of this comparison is fed back into Multisim to control the opening/closure of the switches.

Figure 7. Triangular Wave Generator VI and Block Diagram

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6. Complete System Simulation 

The system simulation graphical interface includes user-defined parameters for the PID control, variable RMS output setpoint, output filter phase offset, and PLL gains. Real-time visualization of the output line voltage compared to the grid voltages is displayed.

Figure 8. Complete System Block Diagram in LabVIEW

Figure 9. VI Showing the System Simulation After 0.02 s

Figure 10. VI Showing the System Simulation After 0.12 s

The simulation results show that after 0.02 s of running the system, the output voltage of the 3-phase inverter is not aligned to the grid voltages since the feedback system is still at its initial stage. The simulation shows that it takes about 0.1 s for the inverter output to align to the grid line voltages.

This unparalleled approach of system simulation that includes all of the dynamics between the analog circuitry and the FPGA control logic enables early evaluation of the system performance as well as saves simulation time and prototyping cost.

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7. Hardware Implementation

The next design stage is to prototype the analog circuitry into hardware and to compile the FPGA IP and load it to target hardware to create an FPGA-based real-time HIL simulation as well as an RCP simulation.

View a complete reference design of this system simulation and rapid prototyping and see a demonstration of a real-time simulation of a 3-phase single-level inverter with RLC filter and load. The real-time HIL simulation is executed in FPGA hardware using LabVIEW at a 1 MHz loop rate. A basic sine-PWM control system is also executed at 500 kHz in the FPGA with an NI 9401 C Series digital I/O module used for communication between the HIL and RCP loops.

You can achieve rapid and easy PCB prototyping using NI Ultiboard.

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Customer Reviews
1 Review | Submit your review

Outdated, will not work with current versions of software  - Oct 25, 2015

The model is described but there are many DLLs referenced that are no longer in the LabVIEW folders so it not possible to load and examine this example. There are not enough details to try and recreate the example in LabVIEW 2015 and Multisim 14.

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