The PXI-1 standard uses the Peripheral Component Interconnect (PCI) bus as a means to exchange data from PXI modules in the chassis to the PXI controller. PCI is a parallel bus that in its most common implementation is 32-bits wide with a frequency of 33 MHz. Data that is acquired by a PXI module is transferred from onboard device memory across the PCI bus, through the I/O controller, across the internal bus and into system memory (RAM). It can then be transferred from system memory, across the internal bus, onto a hard drive(s). Data that is generated by a PXI module follows the opposite path.
Figure 2. Data-streaming architecture of a PCI-based system, implemented between the PXI embedded controller and chassis.
Based upon specifications, the theoretical maximum bandwidth of the PCI bus is 132 MB/s, which translates to 110 MBytes/s of sustainable practical throughput. Since there is only a single link for all the PCI devices to transfer data to and from the host controller, the 110 MB/s of practical bandwidth would be shared across all the devices. Thus, in a PXI system, all the modules in a PXI chassis would share the PCI bus bandwidth. As the performance capabilities of PXI instrumentation are increasing, applications are evolving, and the amount of data that needs to be passed between the modules and the controller continues to increase. In these applications the throughput capabilities of the PCI bus would quickly be exceeded.
PCI Express, an evolution of the PCI bus, maintains software compatibility with PCI but replaces the parallel bus with a high-speed (2.5 Gbits/s) serial bus. PCI Express sends data through differential signal pairs called lanes, which offer 250 MBytes/s of bandwidth per direction per lane. Multiple lanes can be grouped together to form links with typical link widths of x1 (pronounced "by one"), x4, x8, and x16. A x16 Gen1 link provides 4 GBytes/s bandwidth per direction. Moreover, unlike PCI, which shares bandwidth with all devices on the bus, each PCI Express device receives dedicated bandwidth. This allows more number of PXI modules to continuously stream data to and from the embedded controller.
Figure 3. Links are defined by the number of lanes in the group, and are annotated “by N” where N is the number of lanes. For example, PCI Express Gen1 lanes support 250 MB/s compared to PCI Express Gen2 lanes which supports 500 MB/s.
PXI Express chassis are able to accommodate PXI or PXI Express modules, and therefore depending upon the application can easily adapt. However, as instrumentation continues to advance in capabilities the bus technology continues to evolve to provide even more bandwidth capabilities with the announcement of PCI Express 2.0 specification (also known as PCI Express Gen2). The PCI Express Gen2 specification doubles the data transfer rate from Gen1 by doubling the bus bit rate from 2.5 GT/s to 5.0 GT/s while keeping full backward hardware and software compatibility to PCI Express Gen1. PXI Express continuously takes advantage of the latest PCI Express advancements.
For example, the NI PXIe-8133 embedded controller uses PCI Express 2.0 advancements to offer four x4 Gen 2 PCI Express links for interfacing to the PXI chassis backplane. The PXIe-8133 embedded controller offers up to 6.4 GB/s of total system bandwidth, which is twice that the previous generation embedded controller that was based on PCI Express Gen1 links provided.
Figure 4. Taking advantage of PCI Express Gen2, applications can simultaneously stream a larger set of I/O channels, giving the ability to create larger and more complex data record-and-playback applications.
The PXIe-8133 embedded controller connects a x16 Gen2 link from the processor to an onboard PCIe switch. From the onboard PCIe switch that provides four x4 PCIe links to the PXIe-1075 chassis providing 6.4 GB/s of bandwidth. By taking advantage of the latest processor technology, the memory controller on the PXIe-8133 interfaces to two channels of DDR3 1333 MHz DRAM and provides a total memory throughput of 8 GB/s. Through the enabling PCIe Gen2 technology and memory capabilities, the overall system bandwidth increases. With this configuration, pairing the PXIe-8133 with the PXIe-1075 chassis fully exercising the bandwidth of the chassis and the total system bandwidth is 6.4 GB/s. With this architecture, the combination of the chassis and embedded controller now matches the appropriate bandwidth capabilities for the chassis, and can enable even more data throughput as chassis designs evolve.