These user-defined I/O variables transfer single-point data to and from the master controller at each scan cycle, so they are best used for passing processed data from the EtherCAT RIO expansion chassis. For example, in an NIWeek 2009 keynote, presenters used six EtherCAT RIO slave chassis to ring several musical chimes that played a song. The master real-time code controlled the timing of when to ring each distributed chime, but the FPGA on the slave chassis recorded the audio waveform measurements from a microphone and performed a fast Fourier transform (FFT) to get the sound intensity for a specific chime frequency. The slave FPGA then used pulse width modulation (PWM) to control the brightness of a series of LEDs to match the loudness of the chimes. Even without the real-time program running, these LEDs would also react to other loud sounds at the same chime frequencies because of the FPGA logic on the EtherCAT RIO expansion chassis.
Figure 3. This EtherCAT RIO FPGA code was used in an NIWeek 2009 keynote demo to ring several musical chimes that played a song.
In addition to using the LabVIEW FPGA algorithm functions, the slave chassis provides several chassis I/O signals to help customize and synchronize your code. For example, with EtherCAT State you can execute certain FPGA logic during one of the seven EtherCAT states. Therefore, if communication with the master controller ceases, the EtherCAT RIO expansion chassis will enter the safe-operational state and the FPGA code can specify the appropriate safe state behavior. Another set of useful signals is the Output and Input Virtual Point. These two timing signals indicate exactly when each slave updates its output and input values during each scan period. Therefore their rising edges can be used to synchronize FPGA code on multiple EtherCAT RIO expansion chassis. LabVIEW examples are included in the NI-Industrial Communications for EtherCAT driver to demonstrate several advanced FPGA features, such as NI Scan Engine synchronization, specialty digital signals, and asynchronous oversampling.
Figure 4. Synchronize your EtherCAT I/O FPGA code using virtual point timing signals.