Advanced Features of High-Speed Digital I/O devices: Data Delay

Overview

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In high-speed digital communications, because of factors such as setup time and hold time, it might be important to delay the data from the edge of the clock. The different settings and parameters that affect data delay are discussed in the document below.

Contents

Data Delay

With data delay, you can phase shift the acquisition channels, generation channels, and the exported clock. By configuring data and clock positions, you can use your NI digital waveform generator/analyzer for many common applications including, measuring setup and hold times, measuring propagation delays, and maximizing the timing margins among high-speed data transfers. Data delay is available only on Synchronization and Memory Core (SMC)-based products. On these products, you can have one data delay value for generation and one for acquisition only. You can also choose to apply a delay for generation or acquisition per-channel.

This feature is especially important for faster digital signals because at higher rates, clock periods get smaller. Because of these smaller clock periods, it is not enough to just sample at rising or falling edges, because the length that the data is valid might not fall on a rising or a falling edge of the clock. Thus, by shifting the clock by a certain value, you can be sure to sample only when the data is valid and eliminate false data, which might be sampled during the setup and hold times.

For example, you can delay your acquisition channels by 1/64 of your clock period, and delay your generation channels by only 1/256 of your clock period.

Figure 1 shows data delay being used with generation. The data delay tDD(Tx), is added to the Clock to Out Time (tCO) to delay the data by the specified amount.

Figure 1. Data Delay (Generation): The clock is shifted so that it is not aligned with the data, thus ensuring that sampling occurs outside of the setup and hold times. This helps with applications where phenomena such as propagation delay might occur. 

You can use data delay with acquisition as well. In this case, the sample taken is delayed by tDD(Rx). 

Figure 2. Data Delay (Acquisition): You can also use data delay for acquisition of digital signals. The clock can be shifted by a certain amount so that the signal can be sampled in "clean" areas of the digital signal. Using data delay, “bad” sampling, which can be caused by sampling in transition areas, can be prevented.

 

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Data Position Settings

For high-speed digital acquisition and generation, the following are three available data position settings:

•     Sample clock rising edge – Data is generated/acquired on the rising edge of the clock driving the operation.

•     Sample clock falling edge – Data is generated/acquired on the falling edge of the clock driving the operation.

•     Delay from sample clock rising edge – Data is generated/acquired at a specified time after the rising edge of the clock driving the operation. The data position delay resolution depends on your clock frequency.

 

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Data Position Delay Resolution

Most NI digital waveform generator/analyzers have three internal independent delay mechanisms, one for dynamic generation, one for dynamic acquisition, and one for the exported Sample clock. The delay mechanisms are capable of delaying the data and clock positions by up to one full sample clock period, in steps of 1/256 of the Sample clock period, for Sample clock frequencies of 25 MHz and above. Refer to the specifications document for your device for valid frequencies and ranges for delays.

The 6544/5/7/8 devices have a different delay mechanism that results in a variable number of steps depending on the operating frequency.

The 6547/6548 devices support multibank data delay. Each of the 32 channels on this device is assigned to one of three data delay banks (Bank 0, Bank 1, and Bank 2). You can independently configure the data position for each of the 32 channels to sample on the rising or falling edge of the Sample clock or at a specified delay from the Sample clock rising edge. All channels configured to delay data from the Sample clock rising edge and assigned to the same data delay bank must share a data delay value.   For more information regarding multibank data delay refer to the NI Digital Waveform Generator/Analyzer Help manual.  

Operating Frequency Resolution
Table 1 lists the resolution of the delay mechanisms for the frequencies that the NI digital waveform generator/analyzer internal Sample clock can produce. For externally supplied frequencies above 25 MHz that are not listed in this table, the delay resolution is 1/256 of the Sample clock period.

Operating Frequency1

Resolution/Step Size2

200 MHz

20 ps3

100 MHz

39 ps3

66.7 MHz

59 ps3

50 MHz

78 ps

40 MHz

98 ps

33.3 MHz

117 ps

28.6 MHz

137 ps

25 MHz

156 ps

1 Not all operating frequencies will be applicable to your device.
2 These values are not supported for NI 6544/6545/6547/6548 devices. Refer to the device specifications document for more information about the supported step sizes.
3 For NI 656x devices, refer to the device specifications document for more information about the supported step sizes.

Table 1. This table shows the smallest step size/resolution that can be achieved at different operating frequencies of the device.

Minimum Frequency Resolution
When looking at data position delay resolution, it is also important to realize that there is a lower limit to the frequency at which a data delay can be accomplished. Table 2 details the minimum frequencies and their inherent resolutions for each NI digital waveform generator/analyzer.

Device

Minimum Frequency

Resolution

NI 6541/6542

25 MHz

40 ps

NI PXIe-6544/6545

100 Hz*

150 ps

NI PXIe-6547/6548

100 Hz*

150 ps

NI 655x

25 MHz

40 ps

NI 656x

25 MHz

20 ps

* This frequency is only valid when using the internal clock, the minimum frequency with an external clock is 20 MHz.

Table 2. Minimum Frequency and Resolution of HSDIO Devices

What is important to take away from Table 2 is that although the NI 6544/5/7/8 have a much larger resolution compared to other NI digital waveform generator/analyzers, the frequency at which they can support data position delay is much lower.

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Valid Data Delay Ranges

At frequencies higher than 50 MHz, you can legally configure your data delay as any fractional value from 0 to 1 clock period.

At the 25 to 50 MHz frequency range, however, portions of the Sample clock period do not support the data delay. For frequencies between 25 and 50 MHz, you can legally configure data delay as any value from 0 to 1 Sample clock periods except   and  where Tp represents the period of the Sample clock.

 

Figure 3. The image above compares the legal and illegal settings for delaying data position.

 

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Data Delay for Generation

You can use the niHSDIO Configure Data Position Delay VI. The delay is specified by the delay parameter, which is specified as a fraction of the Sample clock period. The position parameter of the niHSDIO Configure Data Position VI or the niHSDIO_ConfigureDataPosition function needs to be set to Delay from Sample Clock Rising Edge as shown in Figure 4.


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Figure 4. This image shows an example of how to use LabVIEW for data delay while generating digital signals using NI high-speed digital I/O boards.

In a text-based environment, you can use the niHSDIO_ConfigureDataPositionDelay function and set the delay parameter as a fraction of the Sample clock period. You can find examples in C programming for HSDIO in Programs»National Instruments»NI-HSDIO»Examples»c.

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Data Delay for Acquisition

In Figure 5, you can see that the niHSDIO Configure Data Position Delay VI can be used for setting the delay as well. Similar to generation, the position parameter of the niHSDIO Configure Data Position VI must be set to Delay from Sample Clock Rising Edge.


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Figure 5. This image shows an example of how to use data delay while acquiring digital signals using NI high-speed digital I/O boards.

In a text-based environment, you can use the niHSDIO_ConfigureDataPosition function and set the position parameter as NIHSDIO_VAL_DELAY_FROM_SAMPLE_CLOCK_RISING_EDGE. You can then use the niHSDIO_ConfigureDataPositionDelay function and set the delay parameter as a fraction of the Sample clock period. You can find examples in C programming for HSDIO in Programs»National Instruments»NI-HSDIO»Examples»c.

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Uses of Data Delay

You can use the data delay feature to compensate for setup and hold times. Consider the setup and hold times of two devices trying to communicate with each other. Consider a case where the NI high-speed DIO device is generating data and providing the clock to a device under test (DUT). If the data lines change exactly with the clock edge, then the NI high-speed DIO device is providing no setup and hold time to the device under test; the times are not stable (unchanging) for some period before and after the clock edge. Data delay provides a solution by allowing the you to shift these signals and to not violate the setup and hold times of the DUT. While setup and hold times are the most common need for data delay, other DUT timing parameters such as settling times and propagation delays may also require data delay.

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Eliminating Round Trip Delay

While performing a stimulus-response application, the time required for data to move from the digital tester, through the cable and DUT, and back to the tester is known as round trip delay (RTD).

One way to account for round trip delay is by exporting a signal with an edge that is synchronous to the start of the stimulus data. This signal should be routed through equal lengths of cable to the acquisition start trigger so that the signal has the same round trip delay as the data. The Data Active event can be used to accomplish this task, since it is synchronous to the start of the stimulus data.

Figure 6 illustrates the signal routing involved in eliminating round trip delay.


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Figure 6. This chart shows how to use data delay in a Digital Test System.

For example, you can export the Data Active event on PFI 1 and route it to PFI 2, which you can configure as the acquisition Start trigger source. Then you can export the generation Sample clock to DDC CLK OUT and configure the acquisition Sample clock source as STROBE. Match your cable lengths so that the signals are routed with the same round trip delay as the data. This method ensures that clocks, control signals, and data signals all arrive at the device at the same time.

Another method to account for round trip delay is to internally route a delayed version of your Data Active event to your acquisition Start trigger. To use this method, you must first know your total round trip delay. Once known, you can set the Data Active Internal Route Delay property or the NIHSDIO_ATTR_DATA_ACTIVE_INTERNAL_ROUTE_DELAY attribute to that number of clock cycles. Then set the Data Position Delay property or the NIHSDIO_ATTR_DATA_POSITION_DELAY attribute to the desired fractional delay.

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Conclusion

The data delay feature of NI-HSDIO is useful for fast digital signals. You can use data delay to eliminate sampling errors that might be caused by factors such as setup and hold times. By phase shifting the clock by fractions of the period, the device can sample at clean regions of the data, which are not affected by factors such as rise time, setup times, and hold times.

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