You create NI VeriStand FPGA personalities using the LabVIEW FPGA Module to modify the personality template that includes the code necessary to interface to your NI VeriStand application. FPGA personalities in NI VeriStand consist of a timing engine, communication loop, and parallel processing loops.
Figure 2. NI VeriStand FPGA Personality Template
The timing engine, which is configured from the NI VeriStand System Explorer, synchronizes the FPGA to the NI VeriStand real-time application as well as other hardware I/O devices in the system. When your NI VeriStand real-time application is deployed, it loads your FPGA personality and the timing engine waits on a start condition from NI VeriStand.
Figure 3. Initializing Timing Engine
Before your real-time application asserts the Start trigger, NI VeriStand sets the parameters for Loop Rate (µs), Write to RTSI, and Use External Timing. These three parameters are responsible for configuring the timing engine’s synchronization mode (master, slave, or no synchronization) and setting the communication rate between your personality and the NI VeriStand real-time application.
The NI VeriStand – Generate PXI FPGA Clock subVI is responsible for generating the clock that times the communication loop discussed below as well as handling synchronization. In master mode, the FPGA times the communication loop with a loop timer running on the FPGA and exports a clock onto the Real-Time System Integration (RTSI) bus to synchronize the other hardware devices. In slave mode, the FPGA monitors the RTSI bus and times the communication loop with the clock captured on RTSI0. In No Synchronization mode, the FPGA times the communication loop with its loop timer and does not export anything onto the RTSI bus.
In addition to performing hardware synchronization, the timing engine allows for synchronization to the NI VeriStand real-time application. Part of the communication loop is shown in Figure 4.
Figure 4. NI VeriStand Synchronization to FPGA
The NI VeriStand – Wait on FPGA Clock subVI acts as the loop timer for the communication loop and waits for the clock from the NI VeriStand – Generate PXI FPGA Clock subVI. In master mode, NI VeriStand also asserts Generate IRQ prior to asserting the Start control. When Generate IRQ is asserted, the NI VeriStand – Synchronize to Host subVI asserts an interrupt on each iteration of the communication loop. If the FPGA is configured as the master, the NI VeriStand real-time application execution is timed by the FPGA via this IRQ signal.
The communication loop is responsible for sending and receiving data to and from the NI VeriStand real-time application. Because NI VeriStand updates channels in a hardware-timed single-point fashion, the FPGA must run its communication loop at the rate specified by the Primary Control Loop in the NI VeriStand Engine. For more information about the NI VeriStand Engine, reference the NI VeriStand Help.
The communication loop is timed by the NI VeriStand – Wait on FPGA Clock subVI, which acts as a loop timer that waits on a clock generated by the NI VeriStand – Generate PXI FPGA Clock subVI discussed previously.
Figure 5. Data Communication Loop
As shown in Figure 5, data in the form of 64-bit packets is sent to the NI VeriStand real-time application via the DMA first-in-first-out memory buffer (FIFO) and data in the form of 64-bit packets is received from the NI VeriStand real-time application via the DMA FIFO.
The first packet sent to NI VeriStand contains information from the NI VeriStand – Synchronize to Host subVI that explains whether the FPGA loop is running late. The other packets sent to the host contain measurement or calculation data performed by the FPGA. The packets are sent by writing to the NI VeriStand – Send Packet to Host subVI inside a For Loop, which is responsible for writing to the DMA_READ FIFO. The DMA_READ FIFO is defined in the Project Explorer, and its depth must be specified to have at least as many elements as packets sent each iteration.
Data is sent to the FPGA via the DMA_WRITE FIFO, which is also defined in the Project Explorer. Its depth must also be specified to have at least as many elements as packets sent each iteration. The DMA_WRITE FIFO is read on the FPGA by the NI VeriStand – Receive Packet from Host subVI placed inside a For Loop. The For Loop must be configured to run the same number of iterations as packets that need to be read each iteration of the While Loop. The packets are then split up and sent to the appropriate parts of your FPGA personality. In Figure 5, the subVIs with yellow title bars signify I/O resources. Any I/O acquired and generated in this loop is synchronous to NI VeriStand and the other hardware devices in the system.
Parallel Processing Loops
Parallel processing loops are the final part of a custom FPGA personality within the NI VeriStand framework. These loops are called parallel because they are not timed from the same clock that times the communication loop to NI VeriStand and the rest of the hardware in the system. These loops may simply be acquiring or generating data on I/O that has custom timing, or they may be responsible for custom measurements and generation such as PWM I/O. They may also be used for coprocessing data sent from NI VeriStand to the FPGA. The example template includes PWM inputs and outputs as shown in Figure 6.
Figure 6. Parallel PWM Loops
As seen in figures 5 and 6, the parallel processing loops send data to/from the communication loop via local variables. The communication loop updates these local variables only at the rate at which it runs, and it sends the current value of a local variable (no buffering) only to the NI VeriStand host. A parallel loop’s data is decimated by the communication loop, but the parallel loop’s timing is not affected by the communication loop.