Table Of Contents

User Data Clock Settings

Version:
    Last Modified: April 18, 2017

    Configure the DAC output at runtime by providing the appropriate User Data 1 value from the User Data Clock Settings table.

    • Timebase Clock—The Timebase Clock is routed to the ADC and the DAC, and is used as a Sample Clock. The Timebase Clock can be provided from the onboard oscillator (which always runs at 1 GHz), the DStarA line, or the CLK IN connector. The Sample Clock is routed to the DAC regardless of the timebase class selected. The timebase is routed to the ADC after being divided down by 4, 2, or 1, depending on whether you select the 1 GHz, 500 MHz, or 250 MHz timebase class, respectively. Select the class that delivers a timebase between 150 MHz and 250 MHz to the ADC.
    • Samples per Channel per Clock Tick)—The samples per channel per clock tick are defined by the rate in MS/s that must be provided to the DAC. For example, if you are using the 1 GHz onboard oscillator and you need to provide 250 MS/s to the DAC, then you must provide two samples per channel per clock tick to the CLIP if you are using the Data Clock, which runs at 125 MHz.
      Number of Samples per Channel per Clock Tick CLIP Signals Required
      4 AO x Data N-3, AO x Data N-2, AO x Data N-1, and AO x Data N
      2 AO x Data N-1 and AO x Data N
      1 AO x Data N
      One sample every two ticks AO x Data N[1]
    • Interpolation Factor—Interpolate the data provided to the DAC to smooth the waveform output. Choose the interpolation factor that matches your needs, as long as the update rate does not exceed 1 GHz. For example, if your data rate is 250 MS/s after configuring the samples per channel per clock tick, an interpolation factor of 4x updates the output of the DAC at a rate of 1 GHz.
    • DAC Clock Divider—The update rate of the DAC's output should match the divided down sample clock that the DAC uses to output the waveform. Since the timebase is routed undivided to the DAC, the DAC Clock Divider configures the clock divider on the DAC to divide the timebase down to the desired Sample Clock rate. For example, if you use the 1 GHz onboard oscillator and the desired update rate is 500 MHz, you must use a DAC clock divider of /2.
    • User Data 1—Once the correct entry for each column has been determined, specify the appropriate value in the User Data 1 column to the User Data 1 signal in the CLIP. If you provide a non-valid value for the User Data 1 signal, the User Command Valid signal returns an error.
    Table 1. User Data Clock Settings
    Timebase Clock[2] Samples per Channel per Clock Tick Interpolation Factor[3] DAC Clock Divider[4] User Data 1
    1GHz Class 4 Bypass Default 0
    1GHz Class 4 Bypass /1 64
    1GHz Class 4 Bypass /2 128
    1GHz Class 4 Bypass /4 192
    1GHz Class 4 2X Default 16
    1GHz Class 4 2X /1 80
    1GHz Class 4 2X /2 144
    1GHz Class 4 2X /4 208
    1GHz Class 4 4X Default 32
    1GHz Class 4 4X /1 96
    1GHz Class 4 4X /2 160
    1GHz Class 4 4X /4 224
    1GHz Class 2 Bypass Default 4
    1GHz Class 2 Bypass /1 68
    1GHz Class 2 Bypass /2 132
    1GHz Class 2 Bypass /4 196
    1GHz Class 2 2X Default 20
    1GHz Class 2 2X /1 84
    1GHz Class 2 2X /2 148
    1GHz Class 2 2X /4 212
    1GHz Class 2 4X Default 36
    1GHz Class 2 4X /1 100
    1GHz Class 2 4X /2 164
    1GHz Class 2 4X /4 228
    1GHz Class 1 Bypass Default 8
    1GHz Class 1 Bypass /1 72
    1GHz Class 1 Bypass /2 136
    1GHz Class 1 Bypass /4 200
    1GHz Class 1 2X Default 24
    1GHz Class 1 2X /1 88
    1GHz Class 1 2X /2 152
    1GHz Class 1 2X /4 216
    1GHz Class 1 4X Default 40
    1GHz Class 1 4X /1 104
    1GHz Class 1 4X /2 168
    1GHz Class 1 4X /4 232
    1GHz Class 1 every 2 clock ticks Bypass Default 12
    1GHz Class 1 every 2 clock ticks Bypass /1 76
    1GHz Class 1 every 2 clock ticks Bypass /2 140
    1GHz Class 1 every 2 clock ticks Bypass /4 204
    1GHz Class 1 every 2 clock ticks 2X Default 28
    1GHz Class 1 every 2 clock ticks 2X /1 92
    1GHz Class 1 every 2 clock ticks 2X /2 156
    1GHz Class 1 every 2 clock ticks 2X /4 220
    1GHz Class 1 every 2 clock ticks 4X Default 44
    1GHz Class 1 every 2 clock ticks 4X /1 108
    1GHz Class 1 every 2 clock ticks 4X /2 172
    1GHz Class 1 every 2 clock ticks 4X /4 236
    500MHz Class 4 Bypass Default 1
    500MHz Class 4 Bypass /1 65
    500MHz Class 4 Bypass /2 129
    500MHz Class 4 Bypass /4 193
    500MHz Class 4 2X Default 17
    500MHz Class 4 2X /1 81
    500MHz Class 4 2X /2 145
    500MHz Class 4 2X /4 209
    500MHz Class 4 4X Default 33
    500MHz Class 4 4X /1 97
    500MHz Class 4 4X /2 161
    500MHz Class 4 4X /4 225
    500MHz Class 2 Bypass Default 5
    500MHz Class 2 Bypass /1 69
    500MHz Class 2 Bypass /2 133
    500MHz Class 2 Bypass /4 197
    500MHz Class 2 2X Default 21
    500MHz Class 2 2X /1 85
    500MHz Class 2 2X /2 149
    500MHz Class 2 2X /4 213
    500MHz Class 2 4X Default 37
    500MHz Class 2 4X /1 101
    500MHz Class 2 4X /2 165
    500MHz Class 2 4X /4 229
    500MHz Class 1 Bypass Default 9
    500MHz Class 1 Bypass /1 73
    500MHz Class 1 Bypass /2 137
    500MHz Class 1 Bypass /4 201
    500MHz Class 1 2X Default 25
    500MHz Class 1 2X /1 89
    500MHz Class 1 2X /2 153
    500MHz Class 1 2X /4 217
    500MHz Class 1 4X Default 41
    500MHz Class 1 4X /1 105
    500MHz Class 1 4X /2 169
    500MHz Class 1 4X /4 233
    500MHz Class 1 every 2 clock ticks Bypass Default 13
    500MHz Class 1 every 2 clock ticks Bypass /1 77
    500MHz Class 1 every 2 clock ticks Bypass /2 141
    500MHz Class 1 every 2 clock ticks Bypass /4 205
    500MHz Class 1 every 2 clock ticks 2X Default 29
    500MHz Class 1 every 2 clock ticks 2X /1 93
    500MHz Class 1 every 2 clock ticks 2X /2 157
    500MHz Class 1 every 2 clock ticks 2X /4 221
    500MHz Class 1 every 2 clock ticks 4X Default 45
    500MHz Class 1 every 2 clock ticks 4X /1 109
    500MHz Class 1 every 2 clock ticks 4X /2 173
    500MHz Class 1 every 2 clock ticks 4X /4 273
    250MHz Class 4 Bypass Default 2
    250MHz Class 4 Bypass /1 66
    250MHz Class 4 Bypass /2 130
    250MHz Class 4 Bypass /4 194
    250MHz Class 4 2X Default 18
    250MHz Class 4 2X /1 82
    250MHz Class 4 2X /2 146
    250MHz Class 4 2X /4 210
    250MHz Class 4 4X Default 34
    250MHz Class 4 4X /1 98
    250MHz Class 4 4X /2 162
    250MHz Class 4 4X /4 226
    250MHz Class 2 Bypass Default 6
    250MHz Class 2 Bypass /1 70
    250MHz Class 2 Bypass /2 134
    250MHz Class 2 Bypass /4 198
    250MHz Class 2 2X Default 22
    250MHz Class 2 2X /1 86
    250MHz Class 2 2X /2 150
    250MHz Class 2 2X /4 214
    250MHz Class 2 4X Default 38
    250MHz Class 2 4X /1 102
    250MHz Class 2 4X /2 166
    250MHz Class 2 4X /4 230
    250MHz Class 1 Bypass Default 10
    250MHz Class 1 Bypass /1 74
    250MHz Class 1 Bypass /2 138
    250MHz Class 1 Bypass /4 202
    250MHz Class 1 2X Default 26
    250MHz Class 1 2X /1 90
    250MHz Class 1 2X /2 154
    250MHz Class 1 2X /4 218
    250MHz Class 1 4X Default 42
    250MHz Class 1 4X /1 106
    250MHz Class 1 4X /2 170
    250MHz Class 1 4X /4 234
    250MHz Class 1 every 2 clock ticks Bypass Default 14
    250MHz Class 1 every 2 clock ticks Bypass /1 78
    250MHz Class 1 every 2 clock ticks Bypass /2 142
    250MHz Class 1 every 2 clock ticks Bypass /4 206
    250MHz Class 1 every 2 clock ticks 2X Default 30
    250MHz Class 1 every 2 clock ticks 2X /1 94
    250MHz Class 1 every 2 clock ticks 2X /2 158
    250MHz Class 1 every 2 clock ticks 2X /4 222
    250MHz Class 1 every 2 clock ticks 4X Default 46
    250MHz Class 1 every 2 clock ticks 4X /1 110
    250MHz Class 1 every 2 clock ticks 4X /2 174
    250MHz Class 1 every 2 clock ticks 4X /4 238
    • 1 You must hold the value provided to AO x Data N constant for two clock cycles when taking one sample every two clock ticks.
    • 2 The internal clock is always 1 GHz. Round the external clock up.
    • 3 The DAC has an on-device PLL that allows you to generate data faster than with an external clock.
    • 4 You can configure the DAC clock so that you can use your intended interpolation mode.

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