Table Of Contents

PXI-5422 Specifications

Version:
    Last Modified: May 4, 2017

    Definitions

    Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

    Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

    • Typical specifications describe the expected performance met by a majority of the models.
    • Nominal specifications describe parameters and attributes that may be useful in operation.

    Specifications are Nominal unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted:

    • Analog filter enabled
    • Signals terminated with 50 Ω
    • Direct path set to 1 Vpk-pk
    • Low-gain amplifier path set to 2 Vpk-pk
    • High-gain amplifier path set to 12 Vpk-pk
    • Sample rate set to 200 MS/s
    • Sample Clock source set to Divide-by-N

    Typical specifications are valid under the following conditions unless otherwise noted:

    • Ambient operating temperature range of 20 ±3 °C

    CH 0

    Number of channels

    1

    Connector type

    SMB jack

    Output Voltage

    Full-scale voltage

    Main output path[1]

    12.00 Vpk-pk to 5.64 mVpk-pk into a 50 Ω load

    Direct output path[2]

    1.000 Vpk-pk to 0.707 Vpk-pk

    DAC Resolution

    16 bits

    Maximum output voltage[3]
    Direct path

    50 Ω load

    ±0.500 Vpk

    1 kΩ load

    ±0.953 Vpk

    Open load

    ±1.000 Vpk

    Low-gain amplifier path

    50 Ω load

    ±1.000 Vpk

    1 kΩ load

    ±1.905 Vpk

    Open load

    ±2.000 Vpk

    High-gain amplifier path

    50 Ω load

    ±6.000 Vpk

    1 kΩ load

    ±11.43 Vpk

    Open load

    ±12.00 Vpk

    Amplitude and Offset

    Amplitude range[4], direct path
    50 Ω load

    Minimum amplitude

    0.707 Vpk-pk

    Maximum amplitude

    1.00 Vpk-pk

    1 kΩ load

    Minimum amplitude

    1.35 Vpk-pk

    Maximum amplitude

    1.91 Vpk-pk

    Open load

    Minimum amplitude

    1.41 Vpk-pk

    Maximum amplitude

    2.00 Vpk-pk

    Amplitude range[4], low-gain amplifier path
    50 Ω load

    Minimum amplitude

    0.00564 Vpk-pk

    Maximum amplitude

    2.00 Vpk-pk

    1 kΩ load

    Minimum amplitude

    0.0107 Vpk-pk

    Maximum amplitude

    3.81 Vpk-pk

    Open load

    Minimum amplitude

    0.0113 Vpk-pk

    Maximum amplitude

    4.00 Vpk-pk

    Amplitude range[4], high-gain amplifier path
    50 Ω load

    Minimum amplitude

    0.0338 Vpk-pk

    Maximum amplitude

    12.0 Vpk-pk

    1 kΩ load

    Minimum amplitude

    0.0644 Vpk-pk

    Maximum amplitude

    22.9 Vpk-pk

    Open load

    Minimum amplitude

    0.0676 Vpk-pk

    Maximum amplitude

    24.0 Vpk-pk

    Amplitude resolution

    <0.06% (0.004 dB) of amplitude range

    Offset range[5]

    Span of ±50% of amplitude range with increments <0.0028% of amplitude range

    Accuracy

    All paths are calibrated for amplitude and gain errors. The low-gain and high-gain amplifier paths are also calibrated for offset errors. Specifications are valid only for high impedance.

    DC accuracy[6]

    Low-gain amplifier and high-gain amplifier paths

    ±0.2% of amplitude range ±0.05% of offset ±500 µV (within ±10 °C of self-calibration temperature)

    ±0.4% of amplitude range ±0.05% of offset ±1 mV (0 °C to 55 °C)

    Direct path

    Gain accuracy

    ±0.2% amplitude range (within ±10 °C of self-calibration temperature)

    ±0.4% amplitude range (0 °C to 55 °C)

    DC offset error

    ±30 mV (0 °C to 55 °C)

    AC amplitude accuracy[7]

    ±1.0% of desired amplitude ±1 mV

    Output Characteristics

    Output impedance

    Software-selectable: 50 Ω or 75 Ω

    Output coupling

    DC

    Output enable

    Software-selectable: When the output path is disabled, the CH 0 output is terminated to ground with a 1 W resistor with a value equal to the selected output impedance

    Maximum output overload

    The CH 0 output can be connected to a 50 Ω, ±12 V (±8 V for the direct path) source without sustaining any damage. No damage occurs if the CH 0 output is shorted to ground indefinitely.

    Waveform summing

    The CH 0 output supports waveform summing among similar paths—specifically, the output terminals of multiple PXI-5422 waveform generators can be connected directly together

    Frequency and Transient Response

    Analog filter[8]

    Software-selectable: 7-pole elliptical filter for image suppression

    Pulse response[9]
    Rise/fall time

    Direct path

    1.0 ns, typical

    Low-gain amplifier path

    2.1 ns, typical

    High-gain amplifier path

    4.8 ns, typical

    Aberration

    Direct path

    16% , typical

    Low-gain amplifier path

    6%, typical

    High-gain amplifier path

    8%, typical

    Figure 1. Normalized Passband Flatness, Direct Path
    Figure 2. Normalized Passband Flatness, Low-Gain Amplifier Path
    Figure 3. Normalized Passband Flatness, High-Gain Amplifier Path
    Figure 4. Pulse Response, Low-Gain Amplifier Path with a 50 Ω Load

    Suggested Maximum Frequencies for Common Functions

    Suggested maximum frequencies[10]
    Sine

    Direct path

    80 MHz

    Low-gain amplifier path

    80 MHz

    High-gain amplifier path

    43 MHz

    Square

    Direct path

    Not recommended

    Low-gain amplifier path

    50 MHz

    High-gain amplifier path

    25 MHz

    Ramp

    Direct path

    Not recommended

    Low-gain amplifier path

    10 MHz

    High-gain amplifier path

    10 MHz

    Triangle

    Direct path

    Not recommended

    Low-gain amplifier path

    10 MHz

    High-gain amplifier path

    10 MHz

    Figure 5. Amplitude Versus Recommended Sine Wave Frequency

    Spectral Characteristics

    Spurious-Free Dynamic Range (SFDR)

    All values are typical and include aliased harmonics. Dynamic range is defined as the difference between the carrier level and the largest spur.

    SFDR with harmonics[11]
    Direct path

    1 MHz

    70 dB

    5 MHz

    70 dB

    10 MHz

    70 dB

    20 MHz

    63 dB

    30 MHz

    57 dB

    40 MHz

    48 dB

    50 MHz

    48 dB

    60 MHz

    47 dB

    70 MHz

    47 dB

    80 MHz

    41 dB

    Low-gain amplifier path

    1 MHz

    65 dB

    5 MHz

    65 dB

    10 MHz

    65 dB

    20 MHz

    64 dB

    30 MHz

    60 dB

    40 MHz

    53 dB

    50 MHz

    53 dB

    60 MHz

    52 dB

    70 MHz

    52 dB

    80 MHz

    52 dB

    High-gain amplifier path

    1 MHz

    66 dB

    5 MHz

    58 dB

    10 MHz

    52 dB

    20 MHz

    49 dB

    30 MHz

    43 dB

    40 MHz

    39 dB

    SFDR without harmonics[11]
    Direct path

    1 MHz

    84 dB

    5 MHz

    84 dB

    10 MHz

    79 dB

    20 MHz

    79 dB

    30 MHz

    72 dB

    40 MHz

    47 dB

    50 MHz

    47 dB

    60 MHz

    46 dB

    70 MHz

    46 dB

    80 MHz

    40 dB

    Low-gain amplifier path

    1 MHz

    79 dB

    5 MHz

    79 dB

    10 MHz

    79 dB

    20 MHz

    79 dB

    30 MHz

    70 dB

    40 MHz

    57 dB

    50 MHz

    52 dB

    60 MHz

    51 dB

    70 MHz

    51 dB

    80 MHz

    51 dB

    High-gain amplifier path

    1 MHz

    76 dB

    5 MHz

    76 dB

    10 MHz

    76 dB

    20 MHz

    76 dB

    30 MHz

    67 dB

    40 MHz

    54 dB

    Average Noise Density[12]

    All values are typical.

    Direct path

    1 Vpk-pk, 4.0 dBm amplitude range

    19.9 nV √Hz , -141 dBm/Hz, -145 dBFS/Hz

    Low-gain amplifier path

    0.06 Vpk-pk, -20.5 dBm amplitude range

    1.3 nV √Hz , -148 dBm/Hz, -144 dBFS/Hz

    0.1 Vpk-pk, -16.0 dBm amplitude range

    2.2 nV √Hz , -148 dBm/Hz, -144 dBFS/Hz

    0.4 Vpk-pk, -4.0 dBm amplitude range

    8.9 nV √Hz , -148 dBm/Hz, -144 dBFS/Hz

    1 Vpk-pk, 4.0 dBm amplitude range

    22.3 nV √Hz , -140 dBm/Hz, -144 dBFS/Hz

    2 Vpk-pk, 10.0 dBm amplitude range

    44.6 nV √Hz , -134 dBm/Hz, -144 dBFS/Hz

    High-gain amplifier path

    4 Vpk-pk, 16.0 dBm amplitude range

    93.8 nV √Hz , -128 dBm/Hz, -144 dBFS/Hz

    12 Vpk-pk, 25.6 dBm amplitude range

    281.5 nV √Hz , -118 dBm/Hz, -144 dBFS/Hz

    Spectrum Performance

    Figure 6. 10 MHz Single-Tone Spectrum, Direct Path, 200 MS/s [13], Typical
    Figure 7. 10.00001 MHz Single-Tone Spectrum, Low-Gain Amplifier Path, 200 MS/s [13], Typical
    Figure 8. Total Harmonic Distortion, Direct Path, Typical
    Figure 9. Total Harmonic Distortion, Low-Gain Amplifier Path, Typical
    Figure 10. Total Harmonic Distortion, High-Gain Amplifier Path, Typical
    Figure 11. Intermodulation Distortion, 200 kHz Separation, Typical
    Figure 12. Direct Path, Two-Tone Spectrum [13], Typical

    Sample Clock

    Sources[141618]

    Internal, Divide-by-N (N ≥ 1)

    Internal, DDS-based, High-Resolution

    External, CLK IN (SMB front panel connector)

    External, DDC CLK IN (DIGITAL DATA & CONTROL front panel connector)

    External, PXI Star Trigger (backplane connector)

    External, PXI_Trig<0..7> (backplane connector)

    Sample Rate Range and Resolution

    Sample rate range

    Divide-by-N

    5 MS/s to 200 MS/s

    High-Resolution

    5 MS/s to 100 MS/s

    >100 MS/s to 200 MS/s

    CLK IN

    5 MS/s to 200 MS/s

    DDC CLK IN

    5 MS/s to 200 MS/s

    PXI Star Trigger

    5 MS/s to 105 MS/s

    PXI_Trig<0..7>

    5 MS/s to 20 MS/s

    Sample rate resolution

    Divide-by-N

    Configurable to (200 MS/s) / N (1 ≤ N ≤ 40)

    High-Resolution

    1.06 µHz

    4.24 µHz

    CLK IN, DDC CLK IN, PXI Star Trigger, and PXI_Trig<0..7>

    Resolution determined by External Clock source. External Sample Clock duty cycle tolerance 40% to 60%.

    Sample Clock Delay Range and Resolution

    Delay adjustment range

    Divide-by-N

    ±1 Sample Clock period

    High-Resolution

    ±1 Sample Clock period

    CLK IN, DDC CLK IN, PXI Star Trigger, and PXI_Trig<0..7>

    0 ns to 7.6 ns

    Delay adjustment resolution

    Divide-by-N

    <5 ps

    High-Resolution ≤100 MHz

    Sample Clock period/16,384

    High-Resolution >100 MHz

    Sample Clock period/4,096

    CLK IN, DDC CLK IN, PXI Star Trigger, and PXI_Trig<0..7>

    <15 ps

    System Phase Noise and Jitter (10 MHz Carrier)[15]

    All values are typical.

    System phase noise density offset
    Divide-by-N

    100 Hz

    -110 dBc/Hz

    1 kHz

    -122 dBc/Hz

    10 kHz

    -138 dBc/Hz

    High-Resolution 100 MS/s[16]

    100 Hz

    -109 dBc/Hz

    1 kHz

    -120 dBc/Hz

    10 kHz

    -120 dBc/Hz

    High-Resolution 200 MS/s[16]

    100 Hz

    -108 dBc/Hz

    1 kHz

    -120 dBc/Hz

    10 kHz

    -122 dBc/Hz

    CLK IN

    100 Hz

    -116 dBc/Hz

    1 kHz

    -130 dBc/Hz

    10 kHz

    -143 dBc/Hz

    PXI Star Trigger[17]

    100 Hz

    -111 dBc/Hz

    1 kHz

    -128 dBc/Hz

    10 kHz

    -136 dBc/Hz

    System output jitter (integrated from 100 Hz to 100 kHz)

    Divide-by-N

    1.5 ps rms

    High-Resolution 100 MS/s[16]

    4.0 ps rms

    High-Resolution 200 MS/s[16]

    4.2 ps rms

    CLK IN

    1.1 ps rms

    PXI Star Trigger[17]

    2.1 ps rms

    External Sample Clock input jitter tolerance

    Cycle-cycle jitter

    ±150 ps

    Period jitter

    ±1 ns

    Sample Clock Exporting

    Destinations[18]

    PFI<0..1> (SMB front panel connectors)

    DDC CLK OUT (DIGITAL DATA & CONTROL front panel connector)

    PXI_Trig<0..6> (backplane connector)

    Maximum frequency

    PFI<0..1>

    200 MHz

    DDC CLK OUT

    200 MHz

    PXI_Trig<0..6>

    20 MHz

    Jitter

    PFI 0

    6 ps rms, typical

    PFI 1

    12 ps rms, typical

    DDC CLK OUT

    60 ps rms, typical

    Duty cycle

    PFI<0..1>

    25% to 65%

    DDC CLK OUT

    35% to 65%

    Onboard Clock (Internal VCXO)

    Source

    Internal Sample Clocks can either be locked to a Reference Clock using a phase-locked loop or derived from the onboard VCXO frequency reference

    Frequency accuracy

    ±25 ppm

    Phase-Locked Loop (PLL) Reference Clock

    Sources[19]

    PXI_CLK10 (backplane connector)

    CLK IN (SMB front panel connector)

    Frequency accuracy

    When using the PLL, the frequency accuracy of the PXI-5422 is solely dependent on the frequency accuracy of the PLL Reference Clock source

    Lock time

    ≤200 ms, typical

    Frequency range[20]

    5 MHz to 20 MHz, in increments of 1 MHz. The default is 10 MHz.

    Duty cycle range

    40% to 60%

    Destinations

    PFI<0..1> (SMB front panel connectors)

    PXI_Trig<0..6> (backplane connector)

    CLK IN

    Connector type

    SMB jack

    Direction

    Input

    Destinations

    Sample Clock

    PLL Reference Clock

    Frequency range

    Sample Clock destination

    5 MHz to 200 MHz

    PLL Reference Clock destination

    5 MHz to 20 MHz

    Input voltage range

    Sine wave

    0.65 Vpk-pk to 2.8 Vpk-pk into 50 Ω (0 dBm to +13 dBm)

    Square wave

    0.2 Vpk-pk to 2.8 Vpk-pk into 50 Ω

    Maximum input overload

    ±10 V

    Input impedance

    50 Ω

    Input coupling

    AC

    PFI 0 and PFI 1

    Connector type

    SMB jack (x2)

    Direction

    Bidirectional

    Frequency range

    DC to 200 MHz

    As an input (trigger)

    Destinations

    Start Trigger

    Maximum input overload

    -2 V to +7 V

    VIH

    2.0 V

    VIL

    0.8 V

    Input impedance

    1 kΩ

    As an output (event)

    Sources

    Sample Clock divided by integer K (1 ≤ K ≤ 4,194,304)

    Sample Clock Timebase (200 MHz) divided by integer M (4M ≤ 4,194,304)

    PLL Reference Clock

    Marker

    Exported Start Trigger (Out Start Trigger)

    Output impedance

    50 Ω

    Maximum output overload

    -2 V to +7 V

    Minimum VOH[21]

    Open load

    2.7 V

    50 Ω load

    1.3 V

    Maximum VOL[21]

    Open load

    0.6 V

    50 Ω load

    0.2 V

    Rise/fall time (20% to 80%)[22]

    ≤2.0 ns

    DIGITAL DATA & CONTROL (DDC)

    Connector type

    68-pin VHDCI female receptacle

    Number of data output signals

    16

    Control signals

    DDC CLK OUT (clock output)

    DDC CLK IN (clock input)

    PFI 2 (input)

    PFI 3 (input)

    PFI 4 (output)

    PFI 5 (output)

    Ground

    23 pins

    Output Signal (Includes Data Outputs, DDC CLK OUT, and PFI<4..5>)

    <
    Low-voltage differential signal (LVDS)[23]

    VOH

    1.3 V, typical

    1.7 V, maximum

    VOL

    0.8 V, minimum

    1.0 V, typical

    Differential output voltage

    0.25 V, minimum

    0.45 V, maximum

    Output common-mode voltage

    1.125 V, minimum

    1.375 V, maximum

    Rise/fall time (20% to 80%)

    0.8 ns, typical

    1.6 ns, maximum

    Output skew[24]

    1 ns, typical

    2 ns, maximum

    Output enable/disable

    Controlled through the software on all data output signals and control signals collectively. When disabled, the output terminals go to a high-impedance state.

    Maximum output overload

    -0.3 V to +3.9 V

    Input Signal (Includes DDC CLK IN and PFI<2..3>)

    Signal type

    Low-voltage differential signal (LVDS)

    Input differential impedance

    100 Ω

    Maximum output overload

    -0.3 V to +3.9 V

    Signal characteristics

    Differential input voltage

    0.1 V, minimum

    0.5 V, maximum

    Input common mode voltage

    0.2 V, minimum

    2.2 V, maximum

    DDC CLK OUT

    Clocking format

    Data outputs and markers change on the falling edge of DDC CLK OUT

    Frequency range

    Refer to the Sample Clock section for more information

    Duty cycle

    35% to 65%

    Jitter

    60 ps rms, typical

    DDC CLK IN

    Clocking format

    DDC data output signals change on the rising edge of DDC CLK IN

    Frequency range

    10 Hz to 200 MHz

    Input duty cycle tolerance

    40% to 60%

    Start Trigger

    Sources

    PFI<0..1> (SMB front panel connectors)

    PFI<2..3> (DIGITAL DATA & CONTROL front panel connector)

    PXI_Trig<0..7> (backplane connector)

    PXI Star Trigger (backplane connector)

    Software (use node or function call)

    Immediate (does not wait for a trigger). The default is Immediate.

    Modes

    Single

    Continuous

    Stepped

    Burst

    Edge detection

    Rising

    Minimum pulse width

    25 ns

    Delay from Start Trigger to CH 0 analog output

    65 Sample Clock periods + 110 ns

    Delay from Start Trigger to digital data output

    41 Sample Clock periods + 110 ns

    Destinations

    A signal used as a trigger can be routed out to any destination listed in the Destinations specification of the Markers section

    Exported trigger delay

    65 ns, typical

    Exported trigger pulse width

    >150 ns

    Markers

    Destinations

    PFI<0..1> (SMB front panel connectors)

    PFI<4..5> (DIGITAL DATA & CONTROL front panel connector)

    PXI_Trig<0..6> (backpane connector)

    Quantity

    One marker per segment

    Quantum

    Marker position must be placed at an integer multiple of four samples

    Width

    >150 ns

    Skew
    PFI<0..1>

    With respect to analog output

    ±2 Sample Clock periods

    PFI<4..5>

    With respect to digital data output

    <2 ns

    PXI_Trig<0..6>

    With respect to analog output

    ±2 Sample Clock periods

    Jitter

    40 ps rms, typical

    Arbitrary Waveform Generation Mode

    Memory usage

    The PXI-5422 uses the Synchronization and Memory Core (SMC) technology in which waveforms and instructions share onboard memory. Parameters, such as number of segments in sequence list, maximum number of waveforms in memory, and number of samples available for waveform storage, are flexible and user-defined.

    Onboard memory size

    8 MB standard

    8,388,608 bytes

    32 MB option

    33,554,432 bytes

    256 MB option

    268,435,456 bytes

    512 MB option

    536,870,912 bytes

    Output modes

    Arbitrary waveform[25]

    Arbitrary sequence[26]

    Minimum waveform size
    Arbitrary waveform mode

    Single Trigger mode

    16 samples

    Continuous Trigger mode

    32 samples

    Stepped Trigger mode

    32 samples

    Burst Trigger mode

    32 samples

    Arbitrary sequence mode[27]

    Single Trigger mode

    16 samples

    Continuous Trigger mode

    192 samples at >50 MS/s

    96 samples at ≤50 MS/s

    Stepped Trigger mode

    192 samples at >50 MS/s

    96 samples at ≤50 MS/s

    Burst Trigger mode

    192 samples at >50 MS/s

    96 samples at ≤50 MS/s

    Loop count

    1 to 16,777,215

    Burst trigger: Unlimited

    Quantum

    Waveform size must be an integer multiple of four samples

    Memory Limits[28]

    Maximum waveform memory, arbitrary waveform mode

    8 MB standard

    4,194,176 samples

    32 MB option

    16,777,088 samples

    256 MB option

    134,217,600 samples

    512 MB option

    268,435,328 samples

    Maximum waveform memory, arbitrary sequence mode[29]

    8 MB standard

    4,194,048 samples

    32 MB option

    16,776,960 samples

    256 MB option

    134,217,472 samples

    512 MB option

    268,435,200 samples

    Maximum waveforms, arbitrary sequence mode[29]

    8 MB standard

    65,000

    Burst trigger: 8,000

    32 MB option

    262,000

    Burst trigger: 32,000

    256 MB option

    2,097,000

    Burst trigger: 262,000

    512 MB option

    4,194,000

    Burst trigger: 524,000

    Maximum segments in a sequence, arbitrary sequence mode[30]

    8 MB standard

    104,000

    Burst trigger: 65,000

    32 MB option

    418,000

    Burst trigger: 262,000

    256 MB option

    3,354,000

    Burst trigger: 2,090,000

    512 MB option

    6,708,000

    Burst trigger: 4,180,000

    Calibration

    Self-calibration

    An onboard, 24-bit ADC and precision voltage reference are used to calibrate the DC gain and offset. The self-calibration is initiated by the user through the software and takes approximately 90 seconds to complete.

    External calibration[31]

    External calibration calibrates the VCXO, voltage reference, DC gain, and offset. Appropriate constants are stored in nonvolatile memory.

    Calibration interval

    Specifications valid within two years of external calibration

    Warm-up time

    15 minutes

    Power

    Typical operation is sine output, with analog filter, 50 Ω termination. 200 MS/s High-Resolution Sample Clock. Digital pattern enabled and terminated, Sample Clock routed to PFI 0 and terminated. Overload operation occurs when CH 0 is shorted to ground.

    +3.3 VDC

    Typical operation

    2 A

    Overload operation

    2 A

    +5 VDC

    Typical operation

    Refer to the following figure

    Overload operation

    2.7 A

    +12 VDC

    Typical operation

    0.46 A

    Overload operation

    0.46 A

    -12 VDC

    Typical operation

    0.01 A

    Overload operation

    0.01 A

    Total power

    Typical operation

    12.2 W + 5 V × 5 V current

    Overload operation

    25.7 W

    Figure 13. 5 V Current Versus Frequency and Amplitude

    Physical Characteristics

    Dimensions

    3U, one-slot, PXI/cPCI module

    21.6 cm × 2.0 cm × 13.0 cm (8.5 in. × 0.8 in. × 5.1 in.)

    Weight

    352 g (12.4 oz)

    Environment

    Maximum altitude

    2,000 m (at 25 °C ambient temperature)

    Pollution Degree

    2

    Indoor use only.

    Operating Environment

    Ambient temperature range

    0 °C to 55 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.) when installed in a PXI-101x or PXI-1000 chassis

    Relative humidity range

    10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Storage Environment

    Ambient temperature range

    -25 °C to 85 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Shock and Vibration

    Shock

    Operating[32]

    30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)

    Storage

    50 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)

    Random vibration

    Operating[32]

    5 Hz to 500 Hz, 0.31 grms (Tested in accordance with IEC 60068-2-64.)

    Nonoperating

    5 Hz to 500 Hz, 2.46 grms (Tested in accordance with IEC 60068-2-64. Test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

    Compliance and Certifications

    Safety

    This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

    • IEC 61010-1, EN 61010-1
    • UL 61010-1, CSA C22.2 No. 61010-1
    spd-note-note
    Note  

    For UL and other safety certifications, refer to the product label or the Online Product Certification section.

    Electromagnetic Compatibility

    This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:
    • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
    • EN 55011 (CISPR 11): Group 1, Class A emissions
    • AS/NZS CISPR 11: Group 1, Class A emissions
    • FCC 47 CFR Part 15B: Class A emissions
    • ICES-001: Class A emissions
    spd-note-note
    Note  

    In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

    spd-note-note
    Note  

    Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

    spd-note-note
    Note  

    For EMC declarations and certifications, refer to the Online Product Certification section.

    CE Compliance

    This product meets the essential requirements of applicable European Directives, as follows:

    • 2014/35/EU; Low-Voltage Directive (safety)
    • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

    Online Product Certification

    Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

    Environmental Management

    NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

    For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

    Waste Electrical and Electronic Equipment (WEEE)

    spd-note-weee
    EU Customers  

    At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    电子信息产品污染控制管理办法(中国RoHS)

    spd-note-china-rohs
    中国客户  

    National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 Depending on the value of the Gain property or NIFGEN_ATTR_GAIN attribute, either the low-gain amplifier or the high-gain amplifier is used when the main output path is selected.
    • 2 The direct path is optimized for intermediate frequency (IF) applications.
    • 3 The maximum output voltage of the PXI-5422 is determined by the amplitude range and the offset range.
    • 4 Amplitude values assume the full scale of the DAC is utilized. NI-FGEN uses waveforms less than the full scale of the DAC to create amplitudes smaller than the minimum value. NI-FGEN compensates for user-specified resistive loads.
    • 5 Offset range is not available on the direct path.
    • 6 For DC accuracy, amplitude range is defined as two times the gain setting. For example, a DC signal with a gain of eight has an amplitude range of 16 V. If this signal has an offset of 1.5, DC accuracy is calculated by the following equation: ±0.2% * (16 V) ± 0.05% * (1.5 V) ± 500µV = ±33.25 mV
    • 7 50 kHz sine wave. Signals terminated with high impedance.
    • 8 Available on low-gain amplifier and high-gain amplifier paths.
    • 9 Analog filter disabled. Measured with a 1 m RG-223 cable.
    • 10 Disable the analog filter for square, ramp, and triangle functions. The minimum frequency is <1 mHz. The value depends on memory size and instrument configuration.
    • 11 Amplitude -1 dBFS. Measured from DC to 100 MHz.
    • 12 Average noise density at small amplitudes is limited by a -148 dBm/Hz noise floor.
    • 13 The noise floor in this figure is limited by the measurement device. Refer to Average Noise Density for more information about this limit.
    • 14 Refer to the Onboard Clock section for more information about internal clock sources.
    • 15 Specified at two times DAC oversampling.
    • 16 High-Resolution specifications vary with sample rate.
    • 17 PXI Star Trigger specification is valid when the sample clock source is locked to PXI_CLK10.
    • 18 Exported Sample Clocks can be divided by integer K (1 ≤ K ≤ 4,194,304).
    • 19 The PLL Reference Clock provides the reference frequency for the PLL.
    • 20 The PLL Reference Clock frequency must be accurate to ±50 ppm.
    • 21 Output drivers are +3.3 V TTL compatible.
    • 22 Load of 10 pF.
    • 23 Tested with 100 Ω differential load, measured with SHC68-C68-D3 multifunction cable, driver and receiver comply with ANSI/TIA/EIA-644.
    • 24 Skew between any two output terminals on the DIGITAL DATA & CONTROL (DDC) front panel connector.
    • 25 In arbitrary waveform mode, a single waveform is selected from the set of waveforms stored in onboard memory and generated.
    • 26 In arbitrary sequence mode, a sequence directs the PXI-5422 to generate a set of waveforms in a specific order. Elements of the sequence are referred to as segments. Each segment is associated with a set of instructions. The instructions identify which waveform is selected from the set of waveforms in memory, how many loops (iterations) of the waveform are generated, and at which sample in the waveform a marker output signal is sent.
    • 27 The minimum waveform size is sample rate dependent in arbitrary sequence mode.
    • 28 All trigger modes except where noted.
    • 29 Condition: One or two segments in a sequence.
    • 30 Condition: Waveform memory is <4,000 samples.
    • 31 Also known as factory calibration.
    • 32 Spectral and jitter specifications could degrade.

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