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    Last Modified: September 19, 2018

    Timing and synchronization module for generating clock and trigger signals, and routing internally or externally generated signals from one location to another.


    Because the PXIe-6674 is not designed for use in the system timing slot, it can not drive CLKIN to PXI_Clk10_IN for overdriving PXI_CLK10 and PXIe_CLK100. The PXIe-6674T is required for this functionality.

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