Table Of Contents

PXIe-5171 Specifications

Version:
    Last Modified: December 6, 2017

    Definitions

    Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

    Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

    • Typical specifications describe the expected performance met by a majority of the models.
    • Nominal specifications describe parameters and attributes that may be useful in operation.

    Specifications are Warranted unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted.

    • All vertical ranges
    • All bandwidths and bandwidth limit filters
    • Sample rate set to 250 MS/s
    • Onboard Sample Clock locked to onboard Reference Clock
    • Calibration IP is used properly when using LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes (instrument design libraries) to create FPGA bitfiles. Refer to the NI Reconfigurable Oscilloscopes Help for more information about the calibration API.

    Warranted specifications are valid under the following conditions unless otherwise noted.

    • Ambient temperature range of 0 °C to 45 °C
    • The PXIe-5171 module is warmed up for 15 minutes at ambient temperature. Warm-up begins after the chassis is powered, the device is recognized by the host, and the ADC clock is configured using either instrument design libraries or the NI-SCOPE device driver.
    • External calibration cycle is maintained
    • The PXI Express chassis fan speed is set to HIGH, the foam fan filters are removed if present, and the empty slots contain PXI chassis slot blockers and filler panels. For more information about cooling, refer to the Maintain Forced-Air Cooling Note to Users available at http://www.ni.com/manuals.
    • External calibration is performed at 23 °C ± 3 °C

    Typical specifications are valid under the following conditions unless otherwise noted.

    • Ambient temperature ranges of 0 °C to 45 °C with a 90% confidence level

    Analog Input

    Number of channels

    8 (simultaneously sampled)

    Input type

    Referenced single-ended

    Connectors

    SMA

    Impedance and Coupling

    Input impedance, typical

    50 Ω ± 1.5%

    Input coupling

    AC, DC

    Figure 1. Voltage Standing Wave Ratio (VSWR), Characteristic
    Figure 2. Input Return Loss, Characteristic

    Voltage Levels

    Full-scale (FS) input range (Vpk-pk)

    0.2 V, 0.4 V, 1 V, 2 V, or 5 V

    Maximum input overload, characteristic[1]

    |Peaks| ≤ 5 V

    Accuracy

    spd-note-caution
    Caution  

    Electromagnetic interference can adversely affect the measurement accuracy of this product. The coaxial channel inputs of this device (CH 0 to CH 7) are not protected for electromagnetic interference. As a result, this device may experience reduced measurement accuracy or other temporary performance degradation when connected cables are routed in an environment with radiated or conducted radio frequency electromagnetic interference. To limit radiated emissions and to ensure that this device functions within specifications in its operational electromagnetic environment, take precautions when designing, selecting, and installing measurement probes and cables.

    Resolution

    14 bits

    Table 1. DC Accuracy [2]
    Input Range Accuracy Drift
    Typical[3] Warranted[4] Characteristic[5]
    Vpk-pk ±(% of |Reading| + % of FS + mV) ±(% of |Reading| + % of FS + mV) ±(% of |Reading| + % of FS + mV) per °C
    0.2 V ±(0.45 + 0.6 + 0.2) ±(0.90 + 0.65 + 0.7) ±(0.015 + 0.002 + 0.004)
    0.4 V ±(0.45 + 0.24 + 0.2) ±(0.80 + 0.25 + 0.7) ±(0.012 + 0.002 + 0.004)
    1 V ±(0.45 + 0.2 + 0.2) ±(0.80 + 0.25 + 0.7) ±(0.010 + 0.002 + 0.004)
    2 V ±(0.40 + 0.2 + 0.2) ±(0.60 + 0.25 + 0.7) ±(0.005 + 0.002 + 0.004)
    5 V ±(0.40 + 0.2 + 0.2) ±(0.55 + 0.25 + 0.7) ±(0.005 + 0.002 + 0.004)
    AC amplitude accuracy[2]

    Accuracy, typical[3]

    ±0.095 dB at 50 kHz

    Accuracy, warranted[4]

    ±0.15 dB at 50 kHz

    Drift, characteristic[5]

    ±0.0013 dB per °C

    Figure 3. Channel-to-Channel Crosstalk, Characteristic [6]

    Bandwidth and Transient Response

    Bandwidth-limiting filter

    100 MHz anti-alias filter

    Bandwidth (-3 dB)[7]

    Anti-alias filter

    100 MHz

    Full bandwidth

    0.2 Vpk-pk input range

    260 MHz

    All other input ranges

    270 MHz

    Table 2. Passband Amplitude Flatness [7]
    Input Frequency Anti-Alias Filter Enabled Full Bandwidth
    <50 MHz -0.5 dB to 0.5 dB -0.5 dB to 0.5 dB
    ≥50 MHz to <90 MHz -1.0 dB to 0.5 dB -0.75 dB to 0.5 dB
    ≥90 MHz to <100 MHz -0.75 dB to 0.5 dB
    ≥100 MHz to <150 MHz -1 dB to 0.5 dB

    AC-coupling cutoff (-3 dB)[8]

    120 kHz, characteristic

    Figure 4. Frequency Response, Anti-Alias Filter Enabled, Characteristic
    Figure 5. Frequency Response (Zoomed), Anti-Alias Filter Enabled, Characteristic
    Figure 6. PXIe-5171 Frequency Response, Full Bandwidth, Characteristic
    Figure 7. PXIe-5171 Frequency Response (Zoomed), Full Bandwidth, Characteristic

    Spectral Characteristics

    Table 3. Spurious-Free Dynamic Range (SFDR), Characteristic [9]
    Input Range (Vpk-pk) Input Frequency Anti-Alias Filter Enabled Full Bandwidth
    0.2 V to 2 V <10 MHz -80.0 dBc -78.0 dBc
    ≥10 MHz to <30 MHz -76.0 dBc -78.0 dBc
    ≥30 MHz to ≤100 MHz -70.0 dBc
    5 V <10 MHz -77.0 dBc -78.0 dBc
    ≥10 MHz to <30 MHz -73.0 dBc -78.0 dBc
    ≥30 MHz to ≤100 MHz -70.0 dBc
    Table 4. Total Harmonic Distortion (THD), Characteristic [10]
    Input Frequency Anti-Alias Filter Enabled Full Bandwidth
    <10 MHz -77.0 -75.0
    ≥10 MHz to <30 MHz -73.0 -75.0
    ≥30 MHz to ≤100 MHz -67.0
    Table 5. Effective Number of Bits (ENOB), Characteristic [9]
    Input Range (Vpk-pk) Input Frequency Anti-Alias Filter Enabled Full Bandwidth
    0.2 V <30 MHz 10.8 9.7
    ≥30 MHz to ≤100 MHz 9.6
    0.4 V <30 MHz 11.0 10.2
    ≥30 MHz to ≤100 MHz 10.1
    All other input ranges <30 MHz 11.0 10.2
    ≥30 MHz to ≤100 MHz 10.2
    Table 6. Second-Order Intermodulation Distortion, Characteristic [11]
    Input Frequency Full Bandwidth
    ≤30 MHz -76.0 dBc
    >30 MHz to ≤70 MHz -75.0 dBc
    >70 MHz≤100 MHz -70.0 dBc
    Table 7. Third-Order Intermodulation Distortion, Characteristic [11]
    Input Frequency Full Bandwidth
    ≤30 MHz -80.0 dBc
    >30 MHz to ≤100 MHz -76.0 dBc
    Figure 8. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 Vpk-pk Input Range, 9.9 MHz Input Tone, Anti-Alias Filter Enabled, Characteristic
    Figure 9. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 Vpk-pk Input Range, 9.9 MHz Input Tone, Full Bandwidth, Characteristic
    Figure 10. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 Vpk-pk Input Range, 99.9 MHz Input Tone, Full Bandwidth, Characteristic
    Figure 11. Two-Tone Spectrum, Each Tone at -3.02 dBm Input Signal at Connector, 1 Vpk-pk Input Range, 9.5 MHz and 10.5 MHz Input Tones, Full Bandwidth, Characteristic
    Figure 12. Two-Tone Spectrum, Each Tone at -3.02 dBm Input Signal at Connector, 1 Vpk-pk Input Range, 99.5 MHz and 100.5 MHz Input Tones, Full Bandwidth, Characteristic

    Noise

    RMS noise, typical[12]

    Anti-alias filter enabled

    0.017% of FS

    Full bandwidth

    0.2 Vpk-pk input range

    0.037% of FS

    0.4 Vpk-pk input range

    0.025% of FS

    All other input ranges

    0.024% of FS

    Table 8. Average Noise Density (dBm/Hz), Typical [12]
    Input Range (Vpk-pk) Anti-Alias Filter Enabled (dBm/Hz) Full Bandwidth (dBm/Hz)
    0.2 V -159.2 dBm/Hz -153.6 dBm/Hz
    0.4 V -153.7 dBm/Hz -150.4 dBm/Hz
    1 V -145.7 dBm/Hz -142.4 dBm/Hz
    2 V -139.7 dBm/Hz -136.4 dBm/Hz
    5 V -131.7 dBm/Hz -128.4 dBm/Hz
    Table 9. Average Noise Density (dBFS/Hz), Typical [12]
    Input Range (Vpk-pk) Anti-Alias Filter Enabled (dBFS/Hz) Full Bandwidth (dBFS/Hz)
    0.2 V 149.2 dBFS/Hz 143.6 dBFS/Hz
    All other input ranges 149.7 dBFS/Hz 146.4 dBFS/Hz
    Table 10. Average Noise Density (nV/√Hz), Typical [12]
    Input Range (Vpk-pk) Anti-Alias Filter Enabled (nV/√Hz) Full Bandwidth (nV/√Hz)
    0.2 V 3.5 nV/√Hz 6.6 nV/√Hz
    0.4 V 6.5 nV/√Hz 9.6 nV/√Hz
    1 V 16.4 nV/√Hz 23.9 nV/√Hz
    2 V 32.7 nV/√Hz 47.9 nV/√Hz
    5 V 81.8 nV/√Hz 119.7 nV/√Hz

    Skew

    Channel-to-channel skew, characteristic

    Anti-alias filter enabled

    <120 ps[13]

    Full bandwidth

    <120 ps

    Horizontal

    ADC Clock

    Sources

    Internal

    Onboard clock

    External

    CLK IN (from front panel AUX I/O connector)

    PXIe_DStarA (from backplane)

    Duty cycle

    45% to 55%

    Frequency

    250 MHz

    Reference Clock

    Sources

    None (internal VCXO)

    CLK IN (from front panel AUX I/O connector)

    PXI_Clk10 (from backplane)

    Duty cycle tolerance

    45% to 55%

    Frequency[14]

    10 MHz

    Onboard Clock

    ADC clock frequency

    250 MHz

    Real-time sample rate range[15]

    3.815 kS/s to 250 MS/s

    Sample Clock jitter, typical

    400 fs RMS[16]

    ADC clock accuracy

    Phase-locked to onboard clock

    ±25.0 ppm

    Phase-locked to external clock

    Equal to the external clock accuracy

    CLK IN

    Source

    AUX I/O front panel connector

    Impedance, characteristic

    50 Ω

    Coupling

    AC

    Input voltage range

    As a 250 MHz sine wave

    1 dBm through 18 dBm

    As a fast slew rate input (square wave, V pk-pk)

    0.4 V to 5 V

    Maximum input overload

    As a 250 MHz sine wave

    20 dBm

    As a fast slew rate input (square wave, V pk-pk)

    6 V

    PXIe_DStarA

    Source

    System timing slot

    Destinations

    ADC clock, FPGA

    PXI_Clk10

    Source

    PXI backplane

    Destination

    Reference Clock

    PXI_Clk100

    Source

    PXI backplane

    Destination

    FPGA

    CLK OUT

    Destination

    AUX I/O front panel connector

    Source

    Reference Clock

    Output impedance, characteristic

    50 Ω

    Logic type

    3.3 V LVCMOS

    Maximum current drive, characteristic

    ±8 mA

    Trigger

    spd-note-note
    Note  

    The following characteristic behaviors are valid when using the device with the NI-SCOPE API. When using instrument design libraries, these characteristics may not be valid.

    Supported trigger

    Reference (Stop) Trigger

    Trigger types

    Edge

    Window

    Hysteresis

    Digital

    Immediate

    Software

    Trigger sources

    CH 0 to CH 7

    PFI <0..7>

    PXI_Trig <0..6>

    Software

    Time resolution

    Analog triggers

    Sample Clock timebase period

    Digital triggers

    8 ns

    Rearm time[17]

    With interpolation

    936 ns

    Without interpolation

    496 ns

    Dead time, characteristic

    40 ns

    Holdoff

    From dead time to [(264 - 1) × Sample Clock timebase period]

    Trigger delay

    From 0 to [(251 - 1) × Sample Clock timebase period]

    Trigger accuracy, characteristic[18]

    0.5% of full scale

    Trigger jitter, characteristic[18]

    15 psrms

    Minimum threshold duration[19]

    Sample Clock period

    Programmable Function Interface (PFI 0..7, AUX I/O Front Panel Connector)

    Connector

    AUX I/O

    Direction

    Bidirectional per channel

    Direction control latency

    25 ns

    As an Input (Trigger)

    Destination

    FPGA diagram

    Start Trigger (Acquisition Arm)

    Reference (Stop) Trigger

    Arm Reference Trigger

    Advance Trigger

    Input impedance, characteristic

    10 kΩ

    VIH

    2 V

    VIL

    0.8 V

    Maximum input overload

    0 V to 3.3 V nominal, 5 V tolerant

    Minimum pulsewidth

    10 ns

    As an Output (Event)

    Sources

    FPGA diagram

    Ready for Start

    Start Trigger (Acquisition Arm)

    Ready for Reference

    Reference (Stop) Trigger

    End of Record

    Ready for Advance

    Advance Trigger

    Done (End of Acquisition)

    Output impedance, characteristic

    50 Ω

    Logic type

    3.3 V CMOS

    Maximum current drive, characteristic

    12 mA

    Minimum pulsewidth

    10 ns

    AUX I/O Connector Specifications

    Connector

    MHDMR

    Voltage output, characteristic

    3.3 V ± 10%

    Maximum current drive, characteristic

    200 mA

    Output impedance, characteristic

    <1 Ω

    Waveform Specifications

    Onboard memory size[20]

    1.5 GB

    Minimum record length

    1 sample

    Number of pretrigger samples

    Zero up to (record length - 1)

    Number of posttrigger samples

    Zero up to record length

    Maximum number of records in onboard memory

    Total onboard memory/(48*number of channels)

    Allocated onboard memory per record[22]

    Roundup(Roundup((Coerced number of samples + Number of samples per sample word) / Number of samples per memory word) * Number of samples per memory word + 3 * Number of samples per memory word) * Bytes Per Sample * Number of channels

    Memory Sanitization

    For information about memory sanitization, refer to the letter of volatility for your device, which is available at ni.com/manuals.

    FPGA

    FPGA support

    Xilinx Kintex-7 XC7K410T FPGA

    Xilinx Kintex-7 XC7K410T FPGA Resources

    Slice registers

    508,400

    Slice look-up tables (LUT)

    254,200

    DSPs

    1,540

    18 Kb block RAMs

    1,590

    spd-note-note
    Note  

    Note that some of these resources are consumed by the logic necessary to operate the device and integrate with software, and are thus out of the control of users.

    Calibration

    External Calibration

    External calibration corrects for gain, offset, and timing errors at all input ranges.

    All calibration constants are stored in nonvolatile memory.

    Self-Calibration

    Self-calibration is done on software command. The calibration corrects for intermodule synchronization errors.

    Calibration Specifications

    Interval for external calibration

    2 years

    Warm-up time[23]

    15 minutes

    Software

    Driver Software

    This device was first supported in LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes 14.0 and NI-SCOPE 15.1. NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the device. NI-SCOPE provides application programming interfaces for many development environments.

    Application Software

    NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

    • LabVIEW
    • LabWindows™/CVI™
    • Measurement Studio
    • Microsoft Visual C/C++
    • .NET (C# and VB.NET)

    Interactive Soft Front Panel and Configuration

    The NI-SCOPE Soft Front Panel (SFP) allows interactive control of the PXIe-5171.

    Interactive control of the PXIe-5171 was first available in NI-SCOPE SFP version 14.0. The NI-SCOPE SFP is included on the instrument design libraries or NI-SCOPE media.

    NI Measurement Automation Explorer (MAX) also provides interactive configuration and test tools for the PXIe-5171. MAX is included on the NI-SCOPE media.

    TClk Specifications

    You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

    Intermodule Synchronization Using NI-TClk for Identical Modules

    Synchronization specifications are valid under the following conditions:

    • All modules are installed in one PXI Express chassis.
    • The NI-TClk driver is used to align the Sample clocks of each module.
    • All parameters are set to identical values for each module.
    • Modules are synchronized without using an external Sample Clock.
    • All filters are disabled.
    spd-note-note
    Note  

    Although you can use NI-TClk to synchronize non-identical SMC-based modules, these specifications apply only to synchronizing identical modules.

    Skew, characteristic[24]

    300 ps

    Skew after manual adjustment, characteristic

    ≤10 ps

    Sample Clock delay/adjustment resolution

    3.5 ps

    Power

    spd-note-note
    Note  

    Power consumed depends on the FPGA image and driver software used. Specifications for instrument design libraries reflect the performance of a device using the FPGA image from the Multirecord Acquisition sample project. Maximum power consumption occurs at highest operating temperature.

    Table 11. PXIe-5171 Power Consumption, Typical
    Instrument Design Libraries NI-SCOPE
    +3.3 VDC 6.4 W 6.3 W
    +12 VDC 16.2W 17.2W
    Total power 22.6 W 23.5 W

    Total maximum power allowed

    38.25 W

    Dimensions and Weight

    Dimensions

    18.5 cm × 2.0 cm × 13.0 cm (7.3 in. × 0.8 in. × 5.1 in.)

    3U, 1 slot, PXI Express Gen 2 x8 Module

    Weight

    484 g (17.1 oz.)

    Environment

    Maximum altitude

    2,000 m (800 mbar) (at 25 °C ambient temperature)

    Pollution Degree

    2

    Indoor use only.

    Operating Environment

    Ambient temperature range

    0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Meets MIL-PRF-28800F Class 3 low temperature limit and MIL-PRF-28800F Class 4 high temperature limit.)

    Relative humidity range

    10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Storage Environment

    Ambient temperature range

    -40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Meets MIL-PRF-28800F Class 3 limits.)

    Relative humidity range

    5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Shock and Vibration

    Operating shock

    30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Meets MIL-PRF-28800F Class 2 limits.)

    Random vibration

    Operating

    5 Hz to 500 Hz, 0.3 grms (Tested in accordance with IEC 60068-2-64.)

    Nonoperating

    5 Hz to 500 Hz, 2.4 grms (Tested in accordance with IEC 60068-2-64. Test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

    Compliance and Certifications

    Safety

    This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

    • IEC 61010-1, EN 61010-1
    • UL 61010-1, CSA C22.2 No. 61010-1
    spd-note-note
    Note  

    For UL and other safety certifications, refer to the product label or the Online Product Certification section.

    Electromagnetic Compatibility

    This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:
    • EN 61326-2-1 (IEC 61326-2-1): Class A emissions; Basic immunity
    • EN 55011 (CISPR 11): Group 1, Class A emissions
    • EN 55022 (CISPR 22): Class A emissions
    • EN 55024 (CISPR 24): Immunity
    • AS/NZS CISPR 11: Group 1, Class A emissions
    • AS/NZS CISPR 22: Class A emissions
    • FCC 47 CFR Part 15B: Class A emissions
    • ICES-001: Class A emissions
    spd-note-note
    Note  

    In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

    spd-note-note
    Note  

    Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

    spd-note-note
    Note  

    For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.

    CE Compliance

    This product meets the essential requirements of applicable European Directives, as follows:

    • 2014/35/EU; Low-Voltage Directive (safety)
    • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

    Online Product Certification

    Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

    Environmental Management

    NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

    For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

    Waste Electrical and Electronic Equipment (WEEE)

    spd-note-weee
    EU Customers  

    At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    电子信息产品污染控制管理办法(中国RoHS)

    spd-note-china-rohs
    中国客户  

    National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 Signals exceeding the maximum input overload may cause damage to the device.
    • 2 Verification of these specifications requires the DC Adjustment Device Temperature (°C) value. If you are using version 14.0 of the software, visit ni.com/info and enter the Info Code exxpmp for information on how to read this value. Otherwise, use instrument design libraries or NI-SCOPE to read the value.
    • 3 When the reading from the Device Temperature sensor is within ±10 °C of the DC Adjustment Device Temperature (°C) value.
    • 4 When the reading from the Device Temperature sensor is within ±38 °C of the DC Adjustment Device Temperature (°C) value. This increased temperature span encompasses the majority of temperature differences between the last external calibration environment and the operating environment.
    • 5 Used to calculate additional temperature error when the difference between the Device Temperature sensor and the DC Adjustment Device Temperature (°C) value is greater than ±10 °C (for typical specifications) or ±38 °C (for warranted specifications).
    • 6 Measured on one channel with test signal applied to another channel, with the same range setting on both channels.
    • 7 Normalized to 50 kHz.
    • 8 With AC coupling enabled, the input impedance is 260 kΩ to ground. Verified using a 50 Ω source.
    • 9 -1 dBFS input signal corrected to FS. 358 Hz resolution bandwidth (RBW).
    • 10 Includes the second through the fifth harmonics. -1 dBFS input signal.
    • 11 Two tones at 1 MHz apart. Each tone is -7 dBFS.
    • 12 Verified using a 50 Ω terminator connected to input.
    • 13 For input frequencies less than 75 MHz.
    • 14 The PLL Reference Clock frequency must be accurate to ±25 ppm.
    • 15 Divide by n decimation from 250 MS/s. For more information about the Sample Clock and decimation, refer to the NI Reconfigurable Oscilloscopes Help at ni.com/manuals.
    • 16 Integrated from 100 Hz to 10 MHz. Includes the effects of the converter aperture uncertainty and the clock circuitry jitter.
    • 17 Trigger interpolation is used when the Enable TDC NI-SCOPE attribute is set to TRUE. Otherwise, trigger interpolation is not used.
    • 18 Analog triggers. For input frequencies less than 90 MHz.
    • 19 Data must exceed each corresponding trigger threshold for at least the minimum duration to ensure analog triggering.
    • 20 Onboard memory is shared among all enabled channels.
    • 21 Number of channels is the number of channels enabled rounded up to the nearest power of two.
    • 22 Descriptions of variables in this equation.
      • Number of samples per sample word = 16 samples / number of channels.
      • Number of samples per memory word = 48 samples / number of channels
      • Coerced number of samples is the number of pre-trigger samples rounded up to the next multiple of the number of samples per sample word + number of post trigger samples rounded up to the next multiple of the number of samples per sample word .
    • 23 Warm-up begins after the chassis is powered, the device is recognized by the host, and the device is configured using the instrument design libraries or NI-SCOPE. Running an included sample project or running self-calibration using NI-MAX will configure the device and start warm-up.
    • 24 Caused by clock and analog path delay differences. No manual adjustment performed. Tested with a NI PXIe-1082 chassis with a maximum slot-to-slot skew of 100 ps. Valid within ±1 °C of self-calibration.

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