PXIe-5171 Specifications

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Last Modified: September 26, 2018

Definitions

Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

Typical specifications describe the performance met by a majority of models.
Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.
Measured specifications describe the measured performance of a representative model.

Specifications are Warranted unless otherwise noted.

Conditions

Specifications are valid under the following conditions unless otherwise noted.

All vertical ranges
Sample rate set to 250 MS/s
Onboard sample clock locked to onboard reference clock
PXIe-5171 module warmed up for 15 minutes at ambient temperature. Warm-up begins after the chassis is powered, the device is recognized by the host, and the ADC clock is configured using either instrument design libraries or the NI-SCOPE device driver.
PXI Express chassis fan speed set to HIGH, foam fan filters removed if present, and empty slots contain PXI chassis slot blockers and filler panels. For more information about cooling, refer to the Maintain Forced-Air Cooling Note to Users available at http://www.ni.com/manuals.
Calibration IP used properly when using LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes (instrument design libraries) to create FPGA bitfiles. Refer to the NI Reconfigurable Oscilloscopes Help for more information about the calibration API.

Warranted specifications are valid under the following conditions unless otherwise noted.

Ambient temperature range of 0 °C to 45 °C
External calibration cycle maintained
External calibration performed at 23 °C ± 3 °C

Typical specifications are valid under the following conditions unless otherwise noted.

Ambient temperature ranges of 0 °C to 45 °C with a 90% confidence level

Nominal and Measured specifications are valid under the following conditions unless otherwise noted.

Room temperature, approximately 23 °C

Vertical

Analog Input

Number of channels	8 (simultaneously sampled)
Input type	Referenced single-ended
Connectors	SMA

Impedance and Coupling

Input impedance	50 Ω ± 1.5%, typical
Input coupling	AC, DC

Figure 1. Voltage Standing Wave Ratio (VSWR), Nominal

Figure 2. Input Return Loss, Nominal

Voltage Levels

Full-scale (FS) input range (V_pk-pk)

0.2 V

0.4 V

1 V

2 V

5 V

Maximum input overload^[1]

|Peaks| ≤ 5 V, nominal

Accuracy

Notice

Electromagnetic interference can adversely affect the measurement accuracy of this product. The coaxial channel inputs of this device (CH 0 to CH 7) are not protected for electromagnetic interference. As a result, this device may experience reduced measurement accuracy or other temporary performance degradation when connected cables are routed in an environment with radiated or conducted radio frequency electromagnetic interference. To limit radiated emissions and to ensure that this device functions within specifications in its operational electromagnetic environment, take precautions when designing, selecting, and installing measurement probes and cables.

Resolution

14 bits

Table 1. DC Accuracy ^[2]

Input Range	Accuracy		Drift
Input Range	Typical^[3]	Warranted^[4]	Nominal^[5]
V_pk-pk	±(% of \|Reading\| + % of FS + mV)	±(% of \|Reading\| + % of FS + mV)	±(% of \|Reading\| + % of FS + mV) per °C
0.2 V	±(0.45 + 0.6 + 0.2)	±(0.90 + 0.65 + 0.7)	±(0.015 + 0.002 + 0.004)
0.4 V	±(0.45 + 0.24 + 0.2)	±(0.80 + 0.25 + 0.7)	±(0.012 + 0.002 + 0.004)
1 V	±(0.45 + 0.2 + 0.2)	±(0.80 + 0.25 + 0.7)	±(0.010 + 0.002 + 0.004)
2 V	±(0.40 + 0.2 + 0.2)	±(0.60 + 0.25 + 0.7)	±(0.005 + 0.002 + 0.004)
5 V	±(0.40 + 0.2 + 0.2)	±(0.55 + 0.25 + 0.7)	±(0.005 + 0.002 + 0.004)

DC accuracy sampling drift, full bandwidth (±% of |Reading| per MHz from 250 MHz)^[6]

±0.03, nominal

AC amplitude accuracy^[2]

Accuracy

±0.095 dB at 50 kHz, typical^[3]

±0.15 dB at 50 kHz, warranted^[4]

Drift^[5]

±0.0013 dB per °C, nominal

Figure 3. Channel-to-Channel Crosstalk, Nominal ^[7]

Bandwidth and Transient Response

Bandwidth-limiting filter

100 MHz anti-alias filter

Bandwidth (-3 dB)^[8]

Anti-alias filter

100 MHz

Full bandwidth
0.2 V_pk-pk input range	260 MHz
All other input ranges	270 MHz

Table 2. Passband Amplitude Flatness ^[8]

Input Frequency	Anti-Alias Filter Enabled	Full Bandwidth
<50 MHz	-0.5 dB to 0.5 dB	-0.5 dB to 0.5 dB
≥50 MHz to <90 MHz	-1.0 dB to 0.5 dB	-0.75 dB to 0.5 dB
≥90 MHz to <100 MHz	—	-0.75 dB to 0.5 dB
≥100 MHz to <150 MHz	—	-1 dB to 0.5 dB

AC-coupling cutoff (-3 dB)^[9]

120 kHz, nominal

Figure 4. Frequency Response, Anti-Alias Filter Enabled, Measured

Figure 5. Frequency Response (Zoomed), Anti-Alias Filter Enabled, Measured

Figure 6. PXIe-5171 Frequency Response, Full Bandwidth, Measured

Figure 7. PXIe-5171 Frequency Response (Zoomed), Full Bandwidth, Measured

Spectral Characteristics

Table 3. Spurious-Free Dynamic Range (SFDR), Nominal ^[10]

Input Range (V_pk-pk)	Input Frequency	Anti-Alias Filter Enabled	Full Bandwidth
0.2 V to 2 V	<10 MHz	-80.0 dBc	-78.0 dBc
	≥10 MHz to <30 MHz	-76.0 dBc	-78.0 dBc
	≥30 MHz to ≤100 MHz	—	-70.0 dBc
5 V	<10 MHz	-77.0 dBc	-78.0 dBc
	≥10 MHz to <30 MHz	-73.0 dBc	-78.0 dBc
	≥30 MHz to ≤100 MHz	—	-70.0 dBc

Table 4. Total Harmonic Distortion (THD), Nominal ^[11]

Input Frequency	Anti-Alias Filter Enabled	Full Bandwidth
<10 MHz	-77.0	-75.0
≥10 MHz to <30 MHz	-73.0	-75.0
≥30 MHz to ≤100 MHz	—	-67.0

Table 5. Effective Number of Bits (ENOB), Nominal ^[10]

Input Range (V_pk-pk)	Input Frequency	Anti-Alias Filter Enabled	Full Bandwidth
0.2 V	<30 MHz	10.8	9.7
0.2 V	≥30 MHz to ≤100 MHz	—	9.6
0.4 V	<30 MHz	11.0	10.2
0.4 V	≥30 MHz to ≤100 MHz	—	10.1
All other input ranges	<30 MHz	11.0	10.2
All other input ranges	≥30 MHz to ≤100 MHz	—	10.2

Table 6. Second-Order Intermodulation Distortion, Nominal ^[12]

Input Frequency	Full Bandwidth
≤30 MHz	-76.0 dBc
>30 MHz to ≤70 MHz	-75.0 dBc
>70 MHz≤100 MHz	-70.0 dBc

Table 7. Third-Order Intermodulation Distortion, Nominal ^[12]

Input Frequency	Full Bandwidth
≤30 MHz	-80.0 dBc
>30 MHz to ≤100 MHz	-76.0 dBc

Figure 8. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 V_pk-pk Input Range, 9.9 MHz Input Tone, Anti-Alias Filter Enabled, Measured

Figure 9. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 V_pk-pk Input Range, 9.9 MHz Input Tone, Full Bandwidth, Measured

Figure 10. Single-Tone Spectrum, 2.98 dBm Input Signal at Connector, 1 V_pk-pk Input Range, 99.9 MHz Input Tone, Full Bandwidth, Measured

Figure 11. Two-Tone Spectrum, Each Tone at -3.02 dBm Input Signal at Connector, 1 V_pk-pk Input Range, 9.5 MHz and 10.5 MHz Input Tones, Full Bandwidth, Measured

Figure 12. Two-Tone Spectrum, Each Tone at -3.02 dBm Input Signal at Connector, 1 V_pk-pk Input Range, 99.5 MHz and 100.5 MHz Input Tones, Full Bandwidth, Measured

Noise

RMS noise^[13]

Anti-alias filter enabled

0.017% of FS, typical

Full bandwidth
0.2 V_pk-pk input range	0.037% of FS, typical
0.4 V_pk-pk input range	0.025% of FS, typical
All other input ranges	0.024% of FS, typical

Table 8. Average Noise Density (dBm/Hz), Typical ^[13]

Input Range (V_pk-pk)	Anti-Alias Filter Enabled (dBm/Hz)	Full Bandwidth (dBm/Hz)
0.2 V	-159.2 dBm/Hz	-153.6 dBm/Hz
0.4 V	-153.7 dBm/Hz	-150.4 dBm/Hz
1 V	-145.7 dBm/Hz	-142.4 dBm/Hz
2 V	-139.7 dBm/Hz	-136.4 dBm/Hz
5 V	-131.7 dBm/Hz	-128.4 dBm/Hz

Table 9. Average Noise Density (dBFS/Hz), Typical ^[13]

Input Range (V_pk-pk)	Anti-Alias Filter Enabled (dBFS/Hz)	Full Bandwidth (dBFS/Hz)
0.2 V	149.2 dBFS/Hz	143.6 dBFS/Hz
All other input ranges	149.7 dBFS/Hz	146.4 dBFS/Hz

Table 10. Average Noise Density (nV/√Hz), Typical ^[13]

Input Range (V_pk-pk)	Anti-Alias Filter Enabled (nV/√Hz)	Full Bandwidth (nV/√Hz)
0.2 V	3.5 nV/√Hz	6.6 nV/√Hz
0.4 V	6.5 nV/√Hz	9.6 nV/√Hz
1 V	16.4 nV/√Hz	23.9 nV/√Hz
2 V	32.7 nV/√Hz	47.9 nV/√Hz
5 V	81.8 nV/√Hz	119.7 nV/√Hz

Skew

Channel-to-channel skew
Anti-alias filter enabled	<120 ps, nominal^[14]
Full bandwidth	<120 ps, nominal

Horizontal

Sample Clock

Sources

Internal

Onboard clock (internal VCXO)

External

AUX I/O CLK IN (front panel MHDMR connector)

PXIe_DStarA (backplane connector)

Sample rate range, real-time^[15]

3.815 kS/s to 250 MS/s

Timebase frequency

250 MHz

Timebase accuracy
Phase-locked to onboard clock	±25.0 ppm
Phase-locked to external clock	Equal to the external clock accuracy

Duty cycle tolerance

45% to 55%

Phase-Locked Loop (PLL) Reference Clock

Sources

Internal

Onboard clock (internal VCXO)

PXI_Clk10 (backplane connector)

External (10 MHz)

AUX I/O CLK IN (front panel MHDMR connector)

Duty cycle tolerance

45% to 55%

External Sample Clock

Source

AUX I/O CLK IN (front panel MHDMR connector)

Impedance

50 Ω, nominal

Coupling

Input voltage range
As a 250 MHz sine wave	1 dBm through 18 dBm
As a fast slew rate input (square wave, V_pk-pk)	0.4 V to 5 V

Maximum input overload
As a 250 MHz sine wave	20 dBm
As a fast slew rate input (square wave, V_pk-pk)	6 V

External Reference Clock In

Source

AUX I/O CLK IN (front panel MHDMR connector)

Impedance

50 Ω, nominal

Coupling

Frequency^[16]

10 MHz

Input voltage range
As a 250 MHz sine wave	1 dBm through 18 dBm
As a fast slew rate input (square wave, V_pk-pk)	6 V

Duty cycle tolerance

45% to 55%

Reference Clock Out

Source	PXI_Clk10 (backplane connector)
Destination	AUX I/O CLK OUT (front panel MHDMR connector)
Output impedance	50 Ω, nominal
Logic type	3.3 V LVCMOS
Maximum current drive	±8 mA, nominal

PXIe_DStarA

Source	System timing slot
Destinations	ADC clock, FPGA

PXI_Clk100

Source	PXI backplane
Destination	FPGA

Trigger

Note

The following characteristic behaviors are valid when using the device with the NI-SCOPE API. When using instrument design libraries, these characteristics may not be valid.

Supported trigger

Reference (Stop) Trigger

Trigger types

Edge

Window

Hysteresis

Digital

Immediate

Software

Trigger sources

CH 0 to CH 7

PFI <0..7>

PXI_Trig <0..6>

Software

Time resolution
Analog triggers	Sample Clock timebase period
Digital triggers	8 ns

Rearm time^[17]
With interpolation	936 ns
Without interpolation	496 ns

Dead time

40 ns, nominal

Holdoff

From dead time to [(2⁶⁴ - 1) × Sample Clock timebase period]

Trigger delay

From 0 to [(2⁵¹ - 1) × Sample Clock timebase period]

Trigger accuracy^[18]

0.5% of full scale, nominal

Trigger jitter^[18]

15 ps_rms, nominal

Minimum threshold duration^[19]

Sample Clock period

Programmable Function Interface (PFI 0..7, AUX I/O Front Panel Connector)

Connector

AUX I/O

Direction

Bidirectional per channel

Direction control latency

25 ns

As an Input (Trigger)
Destination	FPGA diagram Start Trigger (Acquisition Arm) Reference (Stop) Trigger Arm Reference Trigger Advance Trigger
Input impedance	10 kΩ, nominal
V_IH	2 V
V_IL	0.8 V
Maximum input overload	0 V to 3.3 V nominal, 5 V tolerant
Minimum pulse width	10 ns

As an Output (Event)
Sources	FPGA diagram Ready for Start Start Trigger (Acquisition Arm) Ready for Reference Reference (Stop) Trigger End of Record Ready for Advance Advance Trigger Done (End of Acquisition)
Output impedance	50 Ω, nominal
Logic type	3.3 V CMOS
Maximum current drive	12 mA, nominal
Minimum pulse width	10 ns

Power Output (+3.3 V)

Connector	AUX I/O/+3.3 V front panel connector
Voltage output	3.3 V ± 10%, nominal
Maximum current drive	200 mA, nominal
Output impedance	<1 Ω, nominal

Waveform Specifications

Onboard memory size^[20]	1.5 GB
Minimum record length	1 sample
Number of pretrigger samples	Zero up to (record length - 1)
Number of posttrigger samples	Zero up to record length

Figure 13. Maximum Number of Records in Onboard Memory

\frac{total onboard memory}{48 \times number of channels}

where number of channels is the number of channels enabled rounded up to the nearest power of two

Figure 14. Allocated Onboard Memory Per Record

Roundup (Roundup (\frac{coerced number of samples + number of samples per sample word}{number of samples per memory word}) \times number of samples per memory word + 3 \times number of samples per memory word) \times bytes per sample \times number of channels

where

number of samples per sample word = 16 samples / number of channels
number of samples per memory word = 48 samples / number of channels
coerced number of samples is the number of pretrigger samples rounded up to the next multiple of number of samples per sample word + the number of posttrigger samples rounded up to the next multiple of number of samples per sample word
number of channels is the number of channels enabled rounded up to the nearest power of two

Memory Sanitization

For information about memory sanitization, refer to the letter of volatility for your device, which is available at ni.com/manuals.

FPGA

FPGA support

Xilinx Kintex-7 XC7K410T FPGA

Xilinx Kintex-7 XC7K410T FPGA Resources
Slice registers	508,400
Slice look-up tables (LUT)	254,200
DSPs	1,540
18 Kb block RAMs	1,590

Note

Note that some of these resources are consumed by the logic necessary to operate the device and integrate with software, and are thus out of the control of users.

Calibration

External Calibration

External calibration corrects for gain, offset, and timing errors at all input ranges.

All calibration constants are stored in nonvolatile memory.

Self-Calibration

Self-calibration is done on software command. The calibration corrects for intermodule synchronization errors.

Calibration Specifications

Interval for external calibration	2 years
Warm-up time^[21]	15 minutes

Software

Driver Software

This device was first supported in LabVIEW Instrument Design Libraries for Reconfigurable Oscilloscopes 14.0 and NI-SCOPE 15.1. NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the device. NI-SCOPE provides application programming interfaces for many development environments.

Application Software

NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

LabVIEW
LabWindows™/CVI™
Measurement Studio
Microsoft Visual C/C++
.NET (C# and VB.NET)

Interactive Soft Front Panel and Configuration

When you install NI-SCOPE on a 64-bit system, you can monitor, control, and record measurements from the PXIe-5171 using InstrumentStudio.

InstrumentStudio is a software-based front panel application that allows you to perform interactive measurements on several different device types in a single program.

Note

InstrumentStudio is supported only on 64-bit systems. If you are using a 32-bit system, use the NI-SCOPE–specific soft front panel instead of InstrumentStudio.

Interactive control of the PXIe-5171 was first available via InstrumentStudio in NI-SCOPE 18.1 and via the NI-SCOPE SFP in NI-SCOPE 15.1. InstrumentStudio and the NI-SCOPE SFP are included on the NI-SCOPE media.

NI Measurement & Automation Explorer (MAX) also provides interactive configuration and test tools for the PXIe-5171. MAX is included on the driver media.

TClk Specifications

You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

Intermodule Synchronization Using NI-TClk for Identical Modules

Synchronization specifications are valid under the following conditions:

All modules are installed in one PXI Express chassis.
The NI-TClk driver is used to align the Sample clocks of each module.
All parameters are set to identical values for each module.
Modules are synchronized without using an external Sample Clock.
All filters are disabled.

Note

Although you can use NI-TClk to synchronize non-identical SMC-based modules, these specifications apply only to synchronizing identical modules.

Skew^[22]	300 ps, nominal
Skew after manual adjustment	≤10 ps, nominal
Sample Clock delay/adjustment resolution	3.5 ps

Power

Note

Power consumed depends on the FPGA image and driver software used. Specifications for instrument design libraries reflect the performance of a device using the FPGA image from the Multirecord Acquisition sample project. Maximum power consumption occurs at highest operating temperature.

Table 11. PXIe-5171 Power Consumption, Typical

	Instrument Design Libraries	NI-SCOPE
+3.3 VDC	6.4 W	6.3 W
+12 VDC	16.2W	17.2W
Total power	22.6 W	23.5 W

Total maximum power allowed

38.25 W

Dimensions and Weight

Dimensions

18.5 cm × 2.0 cm × 13.0 cm (7.3 in. × 0.8 in. × 5.1 in.)

3U, 1 slot, PXI Express Gen 2 x8 Module

Weight

484 g (17.1 oz.)

Environment

Maximum altitude	2,000 m (800 mbar) (at 25 °C ambient temperature)
Pollution Degree	2

Indoor use only.

Operating Environment

Ambient temperature range	0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Meets MIL-PRF-28800F Class 3 low temperature limit and MIL-PRF-28800F Class 4 high temperature limit.)
Relative humidity range	10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

Storage Environment

Ambient temperature range	-40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2. Meets MIL-PRF-28800F Class 3 limits.)
Relative humidity range	5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

Shock and Vibration

Operating shock

30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Meets MIL-PRF-28800F Class 2 limits.)

Random vibration
Operating	5 Hz to 500 Hz, 0.3 g_rms (Tested in accordance with IEC 60068-2-64.)
Nonoperating	5 Hz to 500 Hz, 2.4 g_rms (Tested in accordance with IEC 60068-2-64. Test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

Compliance and Certifications

Safety Compliance Standards

This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

IEC 61010-1, EN 61010-1
UL 61010-1, CSA C22.2 No. 61010-1

Note

For UL and other safety certifications, refer to the product label or the Product Certifications and Declarations section.

Electromagnetic Compatibility

This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:

EN 61326-2-1 (IEC 61326-2-1): Class A emissions; Basic immunity
EN 55011 (CISPR 11): Group 1, Class A emissions
EN 55022 (CISPR 22): Class A emissions
EN 55024 (CISPR 24): Immunity
AS/NZS CISPR 11: Group 1, Class A emissions
AS/NZS CISPR 22: Class A emissions
FCC 47 CFR Part 15B: Class A emissions
ICES-001: Class A emissions

Note

In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

Note

Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

Note

For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.

CE Compliance

This product meets the essential requirements of applicable European Directives, as follows:

2014/35/EU; Low-Voltage Directive (safety)
2014/30/EU; Electromagnetic Compatibility Directive (EMC)

Product Certifications and Declarations

Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for NI products, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

Environmental Management

NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

Waste Electrical and Electronic Equipment (WEEE)

EU Customers

At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

电子信息产品污染控制管理办法（中国RoHS）

中国客户

National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息，请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

¹ Signals exceeding the maximum input overload may cause damage to the device.
² Verification of these specifications requires the DC Adjustment Device Temperature (°C) value. If you are using version 14.0 of the software, visit ni.com/info and enter the Info Code exxpmp for information on how to read this value. Otherwise, use NI-SCOPE to read the value.
³ When the reading from the Device Temperature sensor is within ±10 °C of the DC Adjustment Device Temperature (°C) value.
⁴ When the reading from the Device Temperature sensor is within ±38 °C of the DC Adjustment Device Temperature (°C) value. This increased temperature span encompasses the majority of temperature differences between the last external calibration environment and the operating environment.
⁵ Used to calculate additional temperature error when the difference between the Device Temperature sensor and the DC Adjustment Device Temperature (°C) value is greater than ±10 °C (for typical specifications) or ±38 °C (for warranted specifications).
⁶ Used to calculate additional DC accuracy error when using an external sample clock of frequency <250 MHz. To calculate the additional error, solve the following for the analog path of interest: $\frac{250 MHz - frequency}{1, 000, 000} \times DC accuracy sampling drift$
⁷ Measured on one channel with test signal applied to another channel, with the same range setting on both channels.
⁸ Normalized to 50 kHz.
⁹ With AC coupling enabled, the input impedance is 260 kΩ to ground. Verified using a 50 Ω source.
¹⁰ -1 dBFS input signal corrected to FS. 358 Hz resolution bandwidth (RBW).
¹¹ Includes the second through the fifth harmonics. -1 dBFS input signal.
¹² Two tones at 1 MHz apart. Each tone is -7 dBFS.
¹³ Verified using a 50 Ω terminator connected to input.
¹⁴ For input frequencies less than 75 MHz.
¹⁵ Divide by n decimation from 250 MS/s. For more information about the sample clock and decimation, refer to the NI Reconfigurable Oscilloscopes Help at ni.com/manuals.
¹⁶ The PLL reference clock frequency must be accurate to ±25 ppm.
¹⁷ Trigger interpolation is used when the Enable TDC NI-SCOPE attribute is set to TRUE. Otherwise, trigger interpolation is not used.
¹⁸ Analog triggers. For input frequencies less than 90 MHz.
¹⁹ Data must exceed each corresponding trigger threshold for at least the minimum duration to ensure analog triggering.
²⁰ Onboard memory is shared among all enabled channels.
²¹ Warm-up begins after the chassis is powered, the device is recognized by the host, and the device is configured using the instrument design libraries or NI-SCOPE. Running an included sample project or running self-calibration using NI-MAX will configure the device and start warm-up.
²² Caused by clock and analog path delay differences. No manual adjustment performed. Tested with an NI PXIe-1082 chassis with a maximum slot-to-slot skew of 100 ps. Valid within ±1 °C of self-calibration.

Table Of Contents

Definitions

Conditions

Vertical

Analog Input

Impedance and Coupling

Voltage Levels

Accuracy

Bandwidth and Transient Response

Spectral Characteristics

Noise

Skew

Horizontal

Sample Clock

Phase-Locked Loop (PLL) Reference Clock

External Sample Clock

External Reference Clock In

Reference Clock Out

PXIe_DStarA

PXI_Clk100

Trigger

Related Topics

Programmable Function Interface (PFI 0..7, AUX I/O Front Panel Connector)

Power Output (+3.3 V)

Waveform Specifications

Memory Sanitization

FPGA

Calibration

External Calibration

Self-Calibration

Related Topics

Calibration Specifications

Software

Driver Software

Related Topics

Application Software

Interactive Soft Front Panel and Configuration

TClk Specifications

Intermodule Synchronization Using NI-TClk for Identical Modules

Power

Dimensions and Weight

Environment

Operating Environment

Storage Environment

Shock and Vibration

Compliance and Certifications

Safety Compliance Standards

Electromagnetic Compatibility

CE Compliance

Product Certifications and Declarations

Environmental Management

Waste Electrical and Electronic Equipment (WEEE)

电子信息产品污染控制管理办法（中国RoHS）

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