Table Of Contents

Reference Clock

Version:
    Last Modified: April 13, 2017

    Sources

    None (internal VCXO)

    CLK IN (from front panel AUX I/O connector)

    PXI_Clk10 (from backplane)

    Duty cycle tolerance

    45% to 55%

    Frequency[1]

    10 MHz

    • 1 The PLL Reference Clock frequency must be accurate to ±25 ppm.

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