Table Of Contents

PXI-5105 Specifications

Version:
    Last Modified: December 13, 2017

    Definitions

    Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

    The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

    • Typical specifications describe the performance met by a majority of models.
    • Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.

    Specifications are Typical unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted.

    • All filter settings
    • All impedance selections
    • Sample clock set to 60 MS/s

    Warranted specifications are valid under the following conditions unless otherwise noted.

    • Temperature range of 0 °C to 55 °C
    • The PXI-5105 module is warmed up for 15 minutes at ambient temperature
    • Calibration cycle is maintained
    • The PXI chassis fan speed is set to HIGH, the foam fan filters are removed if present, and the empty slots contain PXI chassis slot blockers and filler panels. For more information about cooling, refer to the Maintain Forced-Air Cooling Note to Users available at http://www.ni.com/manuals.
    • External calibration is performed at 23 °C ± 3 °C

    Vertical

    Analog Input

    Number of channels

    Eight (simultaneously sampled)

    Input type

    Referenced single-ended

    Connectors

    SMB

    Impedance and Coupling

    Input impedance

    50 Ω

    50 Ω ±2%

    1 MΩ

    1 MΩ ±1% in parallel with a typical capacitance of 50 pF

    Input coupling

    AC[1], DC

    Voltage Levels

    Full-scale (FS) input range

    50 Ω and 1 MΩ

    0.05 V

    0.2 V

    1 V

    6 V

    1 MΩ only

    30 V

    Maximum input overload

    50 Ω

    7 Vrms with |Peaks| ≤10 V

    1 MΩ

    |Peaks| ≤42 V

    Accuracy

    Resolution

    12 bits

    Table 1. DC Accuracy [2]
    Input Impedance Input Range (Vpk-pk) DC Accuracy, Warranted
    50 Ω All ±(1% × Reading + 0.25% of FS + 600 µV)
    1 MΩ 0.05 V ±(1% × Reading + 0.25% of FS + 600 µV)
    0.2 V, 1 V, and 6 V ±(0.65% × Reading + 0.25% of FS + 600 µV)
    30 V ±(0.75% × Reading + 0.25% of FS + 600 µV)

    DC drift

    ±(0.05% Reading + 0.02% of FS + 20 µV) per °C

    Table 2. AC Amplitude Accuracy [2]
    Input Impedance Input Range (Vpk-pk) AC Amplitude Accuracy
    50 Ω All ±0.1 dB (±1.2%) at 50 kHz
    1 MΩ 0.05 V ±0.2 dB (±2.3%) at 50 kHz, warranted
    0.2 V and 1 V ±0.13 dB (±1.5%) at 50 kHz, warranted
    6 V and 30 V ±0.4 dB (±4.7%) at 50 kHz, warranted
    Table 3. Crosstalk [3]
    Input Impedance Input Range (Vpk-pk) Crosstalk
    50 Ω All ≤-80 dB at 1 MHz
    1 MΩ 0.05 V ≤-75 dB at 1 MHz
    0.2 V, 1 V, 6 V, and 30 V ≤-80 dB at 1 MHz

    Bandwidth and Transient Response

    Table 4. Bandwidth ( -3 dB)
    Input Impedance Input Range (Vpk-pk) Bandwidth
    50 Ω 0.05 V 55 MHz
    0.2 V, 1 V, and 6 V 60 MHz
    1 MΩ 0.05 V 35 MHz
    0.2 V, 1 V, 6 V, and 30 V 60 MHz

    Bandwidth-limiting filter

    24 MHz anti-alias filter

    AC-coupling cutoff (-3 dB)[4]

    12 Hz

    Figure 1. Frequency Response, 50 Ω, 1 Vpk-pk Input Range

    Spectral Characteristics

    1 MΩ Spectral Performance[5]

    Table 5. Spurious-Free Dynamic Range (SFDR)
    Input Range (Vpk-pk) SFDR
    0.2 V 70 dBc
    1 V and 6 V 65 dBc
    Table 6. Total Harmonic Distortion (THD)
    Input Range (Vpk-pk) THD
    0.05 V -72 dBc
    0.2 V -75 dBc
    1 V -65 dBc
    6 V -68 dBc
    Table 7. Signal to Noise and Distortion (SINAD)
    Input Range (Vpk-pk) SINAD
    0.05 V 50 dB
    0.2 V 59 dB
    1 V 61 dB
    6 V 59 dB

    1 MΩ Noise

    Table 8. 1 MΩ RMS Noise [6]
    Input Range (Vpk-pk) Full Bandwidth 24 MHz Filter Enabled
    0.05 V 0.18% of FS (90 µV) 0.12% of FS (60 µV)
    0.2 V 0.060% of FS (120 µV) 0.036% of FS (72 µV)
    1 V 0.03% of FS (300 µV) 0.03% of FS (300 µV)
    6 V 0.055% of FS (3.3 mV) 0.036% of FS (2.16 mV)
    30 V 0.03% of FS (9 mV) 0.03% of FS (9 mV)

    50 Ω Spectral Performance

    Table 9. Spurious-Free Dynamic Range (SFDR) [7]
    Input Range (Vpk-pk) SFDR
    0.2 V 72 dBc
    1 V and 6 V 72 dBc
    Table 10. Total Harmonic Distortion (THD) [7]
    Input Range (Vpk-pk) THD
    All -75 dBc
    Table 11. Signal to Noise and Distortion (SINAD) [7]
    Input Range (Vpk-pk) SINAD
    0.05 V 59 dB
    0.2 V to 6 V 62 dB
    Figure 2. PXI-5105 Dynamic Performance, 50 Ω, 1 Vpk-pk, with 24 MHz Filter Enabled
    Figure 3. Representation of PXI-5105 Spectral Noise Density, 50 Ω, 0.05 Vpk-pk, with Anti-Alias Filter Enabled

    50 Ω Noise

    Table 12. 50 Ω RMS Noise [8]
    Input Range (Vpk-pk) Full Bandwidth 24 MHz Filter Enabled
    0.05 V 0.08% of FS (40 µV) 0.038% of FS (19 µV)
    0.2 V 0.04% of FS (80 µV) 0.028% of FS (56 µV)
    1 V 0.03% of FS (300 µV) 0.029% of FS (290 µV)
    6 V 0.03% of FS (1.8 mV) 0.028% of FS (1.68 mV)

    Skew

    Channel-to-channel skew[9]

    24 MHz bandwidth filter disabled

    ≤500 ps

    24 MHz bandwidth filter enabled

    ≤600 ps

    Horizontal

    Sample Clock

    Sources

    Internal

    Onboard clock (internal VCXO)[10]

    External

    PFI 1

    PXI Star

    External frequency range

    4 MHz to 65 MHz

    Exporting[11]

    Destination

    PFI 1

    Maximum frequency

    65 MHz

    Onboard Clock (Internal VCXO)

    Real-time sample rate range[12]

    915.5 S/s to 60 MS/s

    Timebase frequency

    60 MHz

    Timebase accuracy

    Not phase-locked to Reference clock

    ±25 ppm

    Phase-locked to Reference clock

    Equal to the Reference clock accuracy

    Sample clock delay range

    ±1 Sample clock period

    Sample clock delay resolution

    <10 ps

    External Sample Clock

    Sources

    PFI 1

    PXI Star

    Frequency range[13]

    4 MHz to 65 MHz[14]

    Duty cycle tolerance

    45% to 55%

    Phase-Locked Loop (PLL) Reference Clock

    Sources

    PXI_CLK10 (backplane connector)

    PFI 1 (front panel SMB connector)

    Frequency range[15]

    1 MHz to 20 MHz in 1 MHz increments. Default of 10 MHz.

    Duty cycle tolerance

    45% to 55%

    Exported Reference clock destination

    PFI 1

    Triggers

    Reference (Stop) Trigger

    Supported trigger

    Reference (stop) trigger

    Trigger types

    Edge

    Window

    Hysteresis

    Digital

    Immediate

    Software

    Trigger sources

    CH 0 to CH 7

    PFI 1

    PXI_Trig <0..6>

    PXI Star trigger

    Software

    Time resolution

    Sample clock timebase period

    Minimum rearm time[16]

    Internal Onboard clock

    2.4 µs

    External Sample clock

    144 × External clock period

    Holdoff

    From rearm time up to [(232 - 1) × Sample clock timebase period]

    Delay

    From 0 up to [(232 - 1) - Requested posttrigger samples] × (1/Actual sample rate), in seconds

    Analog Trigger

    Trigger types

    Edge

    Window

    Hysteresis

    Sources

    CH 0 to CH 7 (front panel SMB connectors)

    Trigger level range

    100% FS

    Edge trigger sensitivity

    2% FS

    Trigger jitter

    Sample clock timebase period

    Digital Trigger

    Trigger type

    Digital

    Sources

    PFI 1 (front panel SMB connector)

    PXI_TRIG <0..6> (backplane connector)

    PXI Star trigger (backplane connector)

    Programmable Function Interface

    Connector

    PFI 1 (front panel SMB connector)

    Direction

    Bidirectional

    Coupling

    AC

    DC

    As a Sample Clock or Reference Clock

    Input voltage range

    Sine wave

    0.65 Vpk-pk to 2.8 Vpk-pk (0 dBm to 13 dBm)

    Square wave

    0.2 Vpk-pk to 2.8 Vpk-pk

    Maximum input overload

    7 Vrms with |Peaks| ≤10 V

    Input impedance

    50 Ω

    Coupling

    AC

    As an Input (Digital Trigger)

    Destinations

    Start trigger (acquisition arm)

    Reference (stop) trigger

    Arm Reference trigger

    Advance trigger

    Input impedance

    150 kΩ

    VIH

    2.0 V

    VIL

    0.8 V

    Maximum input overload

    -0.5 V, 5.5 V

    Maximum frequency

    65 MHz

    As an Output

    Sources

    Start trigger (acquisition arm)

    Reference (stop) trigger

    End of record

    Done (end of acquisition)

    Sample clock timebase

    Reference clock

    Output impedance

    50 Ω

    Logic type

    3.3 V CMOS

    Maximum drive current

    ±24 mA

    Waveform Specifications

    Onboard memory size options[17]

    16 MB

    128 MB

    512 MB

    Minimum record length

    1 sample

    Number of samples[18]

    Pretrigger

    Zero up to full record length

    Posttrigger

    Zero up to full record length

    Allocated onboard memory per record[19]

    [(Record length in samples × 2 bytes/sample × number of enabled channels) + 480] rounded up to the nearest 128 bytes

    Calibration

    External Calibration

    External calibration calibrates the onboard references used in self-calibration and the external trigger levels. All calibration constants are stored in nonvolatile memory.

    Self-Calibration

    Self-calibration is done on software command. The calibration corrects for gain, offset, triggering, and timing errors for all input ranges.

    Calibration Specifications

    Interval for external calibration

    2 years

    Warm-up time

    15 minutes

    Software

    Driver Software

    Driver support for this device was first available in NI-SCOPE 3.1.

    NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the PXI-5105. NI-SCOPE provides application programming interfaces for many development environments.

    Application Software

    NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

    • LabVIEW
    • LabWindows™/CVI™
    • Measurement Studio
    • Microsoft Visual C/C++
    • .NET (C# and VB.NET)

    Interactive Soft Front Panel and Configuration

    The NI-SCOPE Soft Front Panel (SFP) allows interactive control of the PXI-5105.

    Interactive control of the PXI-5105 was first available in NI-SCOPE SFP version 14.1. The NI-SCOPE SFP is included on the NI-SCOPE media.

    NI Measurement Automation Explorer (MAX) also provides interactive configuration and test tools for the PXI-5105. MAX is included on the NI-SCOPE media.

    TClk Specifications

    You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

    Intermodule SMC Synchronization Using NI-TClk for Identical Modules

    Specifications are valid for modules installed in one NI PXI-1042 chassis. These specifications do not apply to PCI modules. Specifications are valid under the following conditions:

    • All parameters are set to identical values for each SMC-based module.
    • Sample clock set to 60 MS/s.
    • All filters are disabled.
    spd-note-note
    Note  

    Although you can use NI-TClk to synchronize non-identical modules, these specifications apply only to synchronizing identical modules.

    Skew[20]

    500 ps, typical

    Average skew after manual adjustment[21]

    <10 ps, typical

    Sample clock adjustment resolution

    <10 ps, typical

    Power

    Current draw

    +3.3 VDC

    1.5 A, typical

    +5 VDC

    1.7 A, typical

    +12 VDC

    200 mA, typical

    -12 VDC

    25 mA, typical

    Total power

    16.15 W, typical

    Physical

    Dimensions and Weight

    Dimensions

    3U, one-slot, PXI/cPCI module

    21.6 cm × 2.0 cm × 13.0 cm

    (8.5 in × 0.8 in × 5.1 in)

    Weight

    474 g (16.7 oz)

    Figure 4. PXI-5105

    Front Panel Connectors

    Table 13. PXI-5105 Front Panel Connectors
    Label Connector Type Description
    CH 0—CH 7 SMB jack Analog input connection; digitizes data and triggers acquisitions.
    PFI 1 PFI line for trigger input/output, External clock in, Reference clock input/output, and timebase out.

    Environment

    Maximum altitude

    2,000 m (at 25 °C ambient temperature)

    Pollution Degree

    2

    Indoor use only.

    Operating Environment

    Ambient temperature range

    0 °C to 55 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Storage Environment

    Ambient temperature range

    -40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Shock and Vibration

    Operational shock

    30 g peak, half-sine, 11 ms pulse (Tested in accordance with IEC 60068-2-27. Test profile developed in accordance with MIL-PRF-28800F.)

    Random vibration

    Operating

    5 Hz to 500 Hz, 0.31 grms (Tested in accordance with IEC 60068-2-64.)

    Nonoperating

    5 Hz to 500 Hz, 2.46 grms (Tested in accordance with IEC 60068-2-64. Test profile exceeds the requirements of MIL-PRF-28800F, Class 3.)

    Compliance and Certifications

    Safety

    This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

    • IEC 61010-1, EN 61010-1
    • UL 61010-1, CSA C22.2 No. 61010-1
    spd-note-note
    Note  

    For UL and other safety certifications, refer to the product label or the Online Product Certification section.

    Electromagnetic Compatibility

    This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:
    • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
    • EN 55011 (CISPR 11): Group 1, Class A emissions
    • EN 55022 (CISPR 22): Class A emissions
    • EN 55024 (CISPR 24): Immunity
    • AS/NZS CISPR 11: Group 1, Class A emissions
    • AS/NZS CISPR 22: Class A emissions
    • FCC 47 CFR Part 15B: Class A emissions
    • ICES-001: Class A emissions
    spd-note-note
    Note  

    In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

    spd-note-note
    Note  

    Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

    spd-note-note
    Note  

    For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.

    CE Compliance

    This product meets the essential requirements of applicable European Directives, as follows:

    • 2014/35/EU; Low-Voltage Directive (safety)
    • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

    Online Product Certification

    Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

    Environmental Management

    NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

    For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

    Waste Electrical and Electronic Equipment (WEEE)

    spd-note-weee
    EU Customers  

    At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    电子信息产品污染控制管理办法(中国RoHS)

    spd-note-china-rohs
    中国客户  

    National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 AC coupling available on 1 MΩ input only.
    • 2 Within ±5 °C of self-calibration temperature.
    • 3 Measured from one channel to another channel, with same range settings on both channels.
    • 4 AC coupling available on 1 MΩ input only.
    • 5 -1 dBFS input signal. Includes the second through the fifth harmonics. 24 MHz bandwidth filter enabled.
    • 6 Verified using a 50 Ω terminator connected to input.
    • 7 -1 dBFS input signal. Includes the second through the fifth harmonics. 24 MHz bandwidth filter enabled.
    • 8 Verified using a 50 Ω terminator connected to input.
    • 9 10 MHz sine input signal.
    • 10 Internal Sample clock is locked to the Reference clock or derived from the onboard VCXO.
    • 11 You cannot export a decimated Sample clock signal.
    • 12 Divide by n decimation used for all rates less than 60 MS/s. For more information about the Sample clock and decimation, refer to the NI High-Speed Digitizers Help.
    • 13 Divide by n decimation available where 1 ≤ n ≤ 65,535. For more information about the Sample clock and decimation, refer to the NI High-Speed Digitizers Help.
    • 14 The PXI-5105, when using NI-SCOPE 3.2, supports a limited frequency range of 8 MHz to 65 MHz.
    • 15 The PLL Reference clock frequency must be accurate to ±50 ppm.
    • 16 Holdoff set to 0. Onboard Sample clock at maximum rate.
    • 17 Onboard memory is shared between all enabled channels.
    • 18 Single-record and multirecord acquisitions.
    • 19 The maximum number of records is 100,000.
    • 20 Caused by clock and analog path delay differences. No manual adjustment performed.
    • 21 For more information about manual adjustment, refer to the Synchronization Repeatability Optimization topic in the NI-TClk Synchronization Help.

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