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PXIe-5164 Time Interleaved Sampling

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    Last Modified: September 12, 2017

    The PXIe-5164 uses four analog-to-digital converter (ADC) cores per channel, sampling at different equally spaced 250 MHz clock phases. The ADC samples are then recombined to allow for a 1 GS/s effective sample rate with higher resolution than traditionally possible with a single core ADC.

    To reduce the offset, gain, and phase mismatch, this device uses various techniques that reduce the associated spurs.

    • Offset Mismatch Spur—This spur occurs at (1 GS/s)/4 = 250 MHz. The FPGA has a DSP algorithm that dynamically measures and reduces this spur level. In real-time, the DSP algorithm automatically determines if the tone at 250 MHz is caused by the input signal or the ADC Offset Mismatch Spur. If the spur level becomes a significant portion of the input range, the DSP algorithm automatically disables and the data returned is unchanged. This DSP algorithm can be disabled through either the NI-SCOPE API or the instrument design libraries.
    • Gain and Phase Mismatch Spur—These spurs are automatically reduced by DSP inside the ADS54J40 ADC. This algorithm is always running to reduce the effects of gain and phase mismatch.

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