Table Of Contents

Triggers

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    Last Modified: April 25, 2017

    The PXIe-7975 can access eight trigger lines, named PXI_Trig<0..7>, on the PXI Express backplane. You can use these trigger lines to communicate between multiple devices in the same chassis.

    You can also use the following two additional PXI Express triggers.

    • PXIe_DStarB—Trigger line that distributes high-speed, high-quality clock signals from the system timing slot to the peripherals.
    • PXIe_DStarC—Trigger line that sends high-speed, high-quality trigger or clock signals from the peripherals to the system timing slot.

    When developing a high-level VI on the PXIe-7975 that uses triggers, reserve the trigger lines you are using and, to ensure compatibility with other FlexRIO devices, configure trigger pulses to last for at least two clock cycles of the clock on the receiving device. For example, if the clock on the receiving device is 80 MHz, which is a clock period of 12.5 nanoseconds, the trigger line must be constant for at least 25 nanoseconds, which is two cycles of an 80 MHz clock.

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    Note  

    Regardless of the clock speed, pulses on the trigger line must be constant for at least 18 nanoseconds.

    The clocks between a FlexRIO PXI device and another PXI device might not be perfectly synchronized. If you assert a trigger line on a FlexRIO PXI device, you cannot determine at what point in the clock period the trigger registers in the receiving flip-flop. If the trigger arrives during the setup or hold time of the receiving flip-flop, you cannot determine the state of the line for that clock period. Asserting the trigger pulse for two clock cycles ensures that at least one clock cycle on the receiving flip-flop registers as a rising edge and transfers as a trigger.


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