The PXIe-7975 timing is controlled by various base clocks that you can use in your FPGA application.
The following figure shows the clock routing for the PXIe-7975.
|When LabVIEW code downloads to an FPGA target, the FPGA detects whether the 100 MHz oscillator clock is present, and if so, it configures the PLL to lock to the signal.|
|PXI_CLK10——10 MHz system reference clock. You can use this clock as a timebase for running your LabVIEW FPGA VI.|
|PXIe_DStarA—Trigger line that distributes high-speed, high-quality clock signals from the system timing slot to the peripherals. PXIe_DStarA has a configurable frequency for running your LabVIEW code on an FPGA target. You can drive PXIe_DStarA using a timing and synchronization device.|
|The PLL generates the following three clocks:
|Adapter module socketed CLIP can include an external clock source, such as IO Module Clock 0 and IO Module Clock 1. The CLIP you select for your specific adapter module determines how the device uses this clock.|