Table Of Contents

PCI-5152 Specifications

Version:
    Last Modified: December 12, 2017

    Definitions

    spd-note-caution
    Caution  

    If the module has been in use, it may exceed safe handling temperatures and cause burns. Allow the module to cool before removing it from the chassis.

    Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

    The following characteristic specifications describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

    • Typical specifications describe the performance met by a majority of models.
    • Nominal specifications describe an attribute that is based on design, conformance testing, or supplemental testing.

    Specifications in this document are Warranted unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted.

    • All filter settings
    • All impedance selections
    • Sample clock set to 1 GS/s
    • Real-Time Interleaved Sampling (TIS) mode provides a 2 GS/s real-time sample rate for a single channel
    • The module is warmed up for 15 minutes at ambient temperature
    • Calibration cycle is maintained
    • The PXI/PCI chassis fan speed is set to HIGH, the foam fan filters are removed if present, and the empty slots contain chassis slot blockers and filler panels. For more information about cooling, refer to the Maintain Forced-Air Cooling Note to Users.

    Vertical

    Analog Input (Channel 0 and Channel 1)

    Number of channels

    Two (simultaneously sampled)

    Connectors

    BNC

    Impedance and Coupling

    Input Impedance (software-selectable)

    50 Ω

    50 Ω ±1.5%

    1 MΩ

    1 MΩ ±0.75% in parallel with a typical capacitance of 22 pF

    Input coupling

    Software-selectable: AC, DC, GND

    Voltage Levels

    Table 1. Full Scale (FS) Input Range and Programmable Vertical Offset Range
    Range (Vpk-pk) 50 Ω Offset (V) 1 MΩ Offset (V)
    0.1 ±1 ±1
    0.2
    0.4
    1
    2 ±6 ±10
    4 ±5
    10 ±2
    Maximum input overload

    50 Ω

    7 Vrms with |Peaks| ≤10 V

    1 MΩ

    |Peaks| ≤42 V

    Accuracy

    Resolution

    8 bits

    DC accuracy[1]

    0.1 V to 1 V input range

    ±(1.26% of Input + 1.0% of FS + 500 µV)

    2 V to 10 V input range

    ±(1.26% of Input + 1.0% of FS + 5 mV)

    Programmable vertical offset accuracy[1]

    ±0.9% of offset setting

    DC Drift[2]

    0.1 V to 1 V input range

    ±(0.052% of Input + 100 µV) per °C

    2 V to 10 V input range

    ±(0.052% of Input + 1.0 mV) per °C

    Crosstalk
    CH 0 to/from CH 1[3]

    10 MHz

    <-80 dB, typical

    100 MHz

    <-60 dB, typical

    Ext Trig to CH 0 or CH 1[4]

    10 MHz

    <-80 dB, typical

    100 MHz

    <-80 dB, typical

    Bandwidth and Transient Response

    Bandwidth (-3 dB)[5]
    0.1 V input range

    50 Ω

    165 MHz, typical

    135 MHz minimum

    1 MΩ

    135 MHz, typical

    110 MHz minimum

    All other input ranges

    50 Ω

    340 MHz, typical

    300 MHz minimum

    1 MΩ

    300 MHz, typical

    260 MHz minimum

    Rise/fall time[6]
    0.1 V input range

    50 Ω

    2.4 ns, typical

    1 MΩ

    2.8 ns, typical[7]

    All other input ranges

    50 Ω

    1.2 ns, typical

    1 MΩ

    1.4 ns, typical[7]

    Bandwidth limit filter

    20 MHz noise filter

    AC coupling cutoff (-3 dB)[8]

    50 Ω

    106 kHz, typical

    1 MΩ

    12 Hz, typical

    Figure 1. PCI-5152 Frequency Response, 50 Ω, 1 V, Typical
    Figure 2. PCI-5152 Frequency Response, 50 Ω, 1 V Input Range, Typical
    Figure 3. PCI-5152 Step Response, 50 Ω, 10 Vpk-pk through 0.2 Vpk-pk Input Range, Typical
    Figure 4. PCI-5152 Step Response, 50 Ω, 0.1 Vpk-pk Input Range, Typical

    Spectral Characteristics

    ENOB[9]

    Noise filter on

    7.3

    Noise filter off

    7.1

    Signal to Noise and Distortion (SINAD)[9]

    Noise filter on

    45 dB, typical

    Noise filter off

    43 dB, typical

    Figure 5. PCI-5152 Dynamic Performance, 50 Ω, 1 Vpk-pk Range, 9.425 MHz, -1 dBFS Input Signal, Typical
    Figure 6. PCI-5152 TIS Dynamic Performance, 50 Ω, 1 Vpk-pk Range, 9.425 MHz, -1 dBFS Input Signal, Typical

    Noise

    Table 2. RMS Noise [10]
    Range (Vpk-pk) Noise Filter On Noise Filter Off
    0.1 240 µVrms (0.24% FS) 320 µVrms (0.32% FS)
    0.2 480 µVrms (0.24% FS) 600 µVrms (0.30% FS)
    0.4 960 µVrms (0.24% FS) 1.12 mVrms (0.28% FS)
    1 2.4 mVrms (0.24% FS) 2.6 mVrms (0.26% FS)
    2 4.8 mVrms (0.24% FS) 6.0 mVrms (0.30% FS)
    4 9.6 mVrms (0.24% FS) 11.2 mVrms (0.28% FS)
    10 24 mVrms (0.24% FS) 26 mVrms (0.26% FS)

    Channel-to-channel skew

    <100 ps, typical

    Horizontal

    Sample Clock

    Sources

    Internal

    Onboard clock (internal VCSO)[11]

    External

    PFI 0 (front panel SMB connector)

    Onboard Clock (Internal VCSO)

    Sample rate range

    Real-time sampling (single shot)[12]

    15.26 kS/s to 1 GS/s

    TIS[13] mode (single shot)

    2 GS/s (single channel only)

    Random interleaved sampling (RIS) mode[14]

    2 GS/s to 20 GS/s in increments of 1 GS/s (repetitive waveforms only)

    Timebase accuracy

    Not phase-locked to Reference clock

    1 GHz ±30 ppm within ±3 °C of external calibration temperature

    Phase-locked to Reference clock

    Equal to the Reference clock accuracy[15]

    Timebase drift

    Not phase-locked to Reference clock

    ±7 ppm per °C

    Phase-locked to Reference clock

    Equal to Reference clock drift

    Sample clock delay range

    ±1 Sample clock period

    Sample clock delay/adjustment resolution

    ≤5 ps

    External Sample Clock

    Sources

    PFI 0 (front panel SMB connector)

    Frequency range[16]

    350 MHz to 1 GHz

    Duty cycle tolerance

    45% to 55%

    Phase-Locked Loop (PLL) Reference Clock

    Sources

    RTSI 7

    PFI 0 (front panel SMB connector)

    Frequency range[17]

    1 MHz to 20 MHz in 1 MHz increments

    Default: 10 MHz

    Duty cycle tolerance

    45% to 55%

    Exported Reference clock destinations

    RTSI <0..7>

    PFI 1 (front panel SMB connector)

    Sample Clock and Reference Clock Input (PFI 0, Front Panel Connector)

    Input voltage range

    Sine wave: 0.65 Vpk-pk to 2.8 Vpk-pk

    (0 dBm to 13 dBm)

    Maximum input overload

    7 Vrms with |Peaks| ≤10 V

    Impedance

    50 Ω

    Coupling

    AC

    Reference Clock Output (PFI 1, Front Panel Connector)

    Output impedance

    50 Ω

    Logic type

    3.3 V CMOS, except when exporting 5 V

    Maximum drive current

    ±24 mA

    Trigger

    Trigger types[18]

    Edge

    Window

    Hysteresis

    Video

    Digital

    Immediate

    Software

    Trigger sources

    CH 0

    CH 1

    TRIG

    PFI <0..1>

    RTSI <0..6>

    Software

    Time resolution

    Onboard clock, time-to-digital conversion circuit (TDC) on

    5 ps

    Onboard clock, TDC off

    1 ns

    External clock, TDC off

    External clock period

    Minimum rearm time[19]

    TDC on

    8 µs

    TDC off

    1 µs

    Holdoff

    From rearm time up to [(232 - 1) × Sample clock period]

    Trigger delay

    From 0 up to [(235 - 1) - Posttrigger samples] × (1/Sample rate), in seconds

    Analog Trigger

    Trigger types

    Edge

    Window

    Hysteresis

    Sources

    CH 0 (front panel BNC connector)

    CH 1 (front panel BNC connector)

    TRIG (front panel BNC connector)

    Trigger level range[20]

    CH 0, CH 1

    100% FS

    TRIG (External trigger)

    ±5 V

    Voltage resolution

    8 bits (1 in 256)

    Trigger level accuracy[21]

    CH 0, CH 1

    ±5% FS up to 10 MHz, typical

    TRIG (External trigger)

    ±1 V (±10% FS) up to 10 MHz, typical

    Edge trigger sensitivity[20]

    CH 0, CH 1

    10% FS

    TRIG (External trigger, Vpk-pk)

    0.5 V

    Trigger jitter[21]

    ≤10 psrms, typical

    ≤20 psrms, maximum

    Trigger filters

    Low frequency reject (LF)

    50 kHz

    High frequency reject (HF)

    50 KHz

    Digital Trigger

    Trigger type

    Digital

    Sources

    RTSI <0..6>

    PFI <0..1> (front panel SMB connector)

    External Trigger Input (Front Panel Connector)

    Connector

    BNC

    Impedance

    1 MΩ in parallel with a typical capacitance of 22 pF

    Coupling

    AC, DC

    AC coupling cutoff (-3 dB)

    12 Hz

    Input voltage range

    ±5 V

    Maximum input overload

    |Peaks| ≤42 V

    PFI 0 and PFI 1 (Programmable Function Interface, Front Panel Connectors)

    Connector

    SMB jack

    Direction

    Bidirectional

    As an Input (Trigger)

    Destination

    Start trigger (acquisition arm)

    Reference (stop) trigger

    Arm reference trigger

    Advance trigger

    Input impedance

    150 kΩ

    VIH

    2.0 V

    VIL

    0.8 V

    Maximum input overload

    -0.5 V to 5.5 V

    Maximum frequency

    25 MHz

    As an Output (Event)

    Sources

    Start trigger (acquisition arm)

    Reference (stop) trigger

    End of record

    Done (end of acquisition)

    Probe compensation[22]

    Output impedance

    50 Ω

    Logic type

    3.3 V CMOS

    Maximum drive current

    ±24 mA

    Maximum frequency

    25 MHz

    Waveform Specifications

    Table 3. Onboard Memory Size
    Real-Time and RIS Modes Real-Time TIS Mode
    8 MB standard (8 MS) per channel 8 MB standard (8 MS)
    64 MB option (64 MS) per channel 64 MB option (64 MS)
    256 MB option (256 MS) per channel 256 MB option (256 MS)
    512 MB option (512 MS)

    Minimum record length

    1 sample

    Number of pretrigger samples

    Zero up to full record length

    Number of posttrigger samples

    Zero up to full record length

    Maximum number of records in onboard memory[24]

    8 MB per channel

    32,768

    64 MB per channel

    100,000

    256 MB per channel

    100,000

    512 MB per channel

    100,000

    Allocated onboard memory per record

    [(Record length × 1 byte/sample) + 400 bytes] rounded up to next multiple of 128 bytes

    Calibration

    External Calibration

    External calibration calibrates the VCSO and the voltage reference. All calibration constants are stored in nonvolatile memory.

    Self-Calibration

    Self-calibration is done on software command. The calibration corrects for gain, offset, triggering, and timing errors for all input ranges.

    Calibration Specifications

    Interval for external calibration

    2 years

    Warm-up time

    15 minutes

    Software

    Driver Software

    Driver support for the PCI-5152 was first available in NI-SCOPE 3.3.

    NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the PCI-5152. NI-SCOPE provides application programming interfaces for many development environments.

    Application Software

    NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

    • LabVIEW
    • LabWindows™/CVI™
    • Measurement Studio
    • Microsoft Visual C/C++
    • .NET (C# and VB.NET)

    Interactive Soft Front Panel and Configuration

    The NI-SCOPE Soft Front Panel (SFP) allows interactive control of the PCI-5152.

    Interactive control of the PCI-5152 was first available in NI-SCOPE SFP version 3.3. The NI-SCOPE SFP is included on the NI-SCOPE media.

    NI Measurement Automation Explorer (MAX) also provides interactive configuration and test tools for the PCI-5152. MAX is included on the NI-SCOPE media.

    TClk Specifications

    You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

    Intermodule SMC Synchronization Using NI-TClk for Identical Modules

    Synchronization specifications are valid under the following conditions:

    • All modules are installed in one NI PXI-1042 chassis
    • The NI-TClk driver is used to align the Sample clocks of each module
    • All parameters are set to identical values for each module
    • Modules are synchronized without using an external Sample clock
    • Sample clock set to 1 GS/s and all filters are disabled
    spd-note-note
    Note  

    Although you can use NI-TClk to synchronize non-identical SMC-based modules, these specifications apply only to synchronizing identical modules.

    Skew

    500 ps, typical

    Skew after manual adjustment

    ≤5 ps, typical

    Sample clock delay/adjustment resolution

    ≤5 ps, typical

    Power

    Current draw

    +3.3 VDC

    2.5 A

    +5 VDC

    2.4 A

    +12 VDC

    200 mA

    -12 VDC

    0 A

    Total power

    22.65 W

    Physical

    Dimensions

    35.5 cm x 2.0 cm x 11.3 cm

    (14.0 in x 0.8 in x 4.4 in)

    Weight

    445 g (15.7 oz)

    Figure 7. PCI-5152 Dimensions

    Environment

    Environment

    Maximum altitude

    2,000 m (at 25 °C ambient temperature)

    Pollution Degree

    2

    Indoor use only.

    Operating Environment

    Ambient temperature range

    0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Storage Environment

    Ambient temperature range

    -40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Compliance and Certifications

    Safety

    This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

    • IEC 61010-1, EN 61010-1
    • UL 61010-1, CSA C22.2 No. 61010-1
    spd-note-note
    Note  

    For UL and other safety certifications, refer to the product label or the Online Product Certification section.

    Electromagnetic Compatibility

    This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:
    • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
    • EN 55011 (CISPR 11): Group 1, Class A emissions
    • EN 55022 (CISPR 22): Class A emissions
    • EN 55024 (CISPR 24): Immunity
    • AS/NZS CISPR 11: Group 1, Class A emissions
    • AS/NZS CISPR 22: Class A emissions
    • FCC 47 CFR Part 15B: Class A emissions
    • ICES-001: Class A emissions
    spd-note-note
    Note  

    In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

    spd-note-note
    Note  

    Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

    spd-note-note
    Note  

    For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.

    CE Compliance

    This product meets the essential requirements of applicable European Directives, as follows:

    • 2014/35/EU; Low-Voltage Directive (safety)
    • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

    Online Product Certification

    Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

    Environmental Management

    NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

    For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

    Waste Electrical and Electronic Equipment (WEEE)

    spd-note-weee
    EU Customers  

    At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    电子信息产品污染控制管理办法(中国RoHS)

    spd-note-china-rohs
    中国客户  

    National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 Programmable vertical offset = 0 V. Within ±5 °C of self-calibration temperature.
    • 2 Use DC drift to calculate errors when temperature changes more than ±5 °C since the last self-calibration.
    • 3 Measured on one channel with test signal applied to another channel, with same range setting on both channels.
    • 4 10 V signal applied to external trigger channel. Applies to all ranges on CH 0 and CH 1.
    • 5 Bandwidth for 0 to 30 °C. Reduce by 0.25% per °C above 30 °C for all input ranges. Filter off for all input ranges.
    • 6 Filter off.
    • 7 50 Ω terminator connected to front panel BNC connector.
    • 8 50 Ω source assumed.
    • 9 1 V input range, 10 MHz, -1 dBFS input signal. Includes the 2nd through the 5th harmonics.
    • 10 50 Ω terminator connected to input.
    • 11 Internal Sample clock is locked to the Reference clock or derived from the onboard VCSO.
    • 12 Divide by n decimation used for all rates less than 1 GS/s.
    • 13 TIS is a type of real-time sampling that is sometimes called ping-pong.
    • 14 RIS is a type of equivalent-time sampling.
    • 15 Refer to your chassis specifications for the Reference clock accuracy.
    • 16 Divide by n decimation available where 1 ≤ n ≤ 65,535. For more information about the Sample clock and decimation, refer to the NI High-Speed Digitizers Help.
    • 17 The PLL Reference clock frequency must be accurate to ±50 ppm.
    • 18 Refer to the following sources and the NI High-Speed Digitizers Help for more information about which sources are available for each trigger type.
    • 19 Holdoff set to 0. Onboard Sample clock at maximum rate.
    • 20 DC to 300 MHz.
    • 21 Within ±5 °C of self-calibration temperature.
    • 22 1 kHz, 50% duty cycle square wave. PFI 1 only.
    • 23 Single-record mode and multiple-record mode.
    • 24 It is possible to exceed these numbers if you fetch records while acquiring data. For more information, refer to the High-Speed Digitizers Help.

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