Table Of Contents

PCI-5124 Specifications

Version:
    Last Modified: February 24, 2017

    Definitions

    Warranted specifications describe the performance of a model under stated operating conditions and are covered by the model warranty.

    Characteristics describe values that are relevant to the use of the model under stated operating conditions but are not covered by the model warranty.

    • Typical specifications describe the expected performance met by a majority of the models.
    • Nominal specifications describe parameters and attributes that may be useful in operation.

    Specifications are Warranted unless otherwise noted.

    Conditions

    Specifications are valid under the following conditions unless otherwise noted.

    • All filter settings
    • All impedance selections
    • Sample clock set to 200 MS/s using onboard clock
    • The PCI-5124 module is warmed up for 15 minutes at ambient temperature.
    • Calibration cycle is maintained.
    • External calibration is performed at 23 °C ± 5 °C
    spd-note-hot
    Hot Surface  

    If the PCI-5124 has been in use, it may exceed safe handling temperatures and cause burns. Allow the PCI-5124 to cool before removing it from the chassis.

    spd-note-caution
    Caution  

    To ensure the specified EMC performance, operate this product only with double-shielded cables (for example, RG-233/U or equivalent) and shielded accessories.

    spd-note-caution
    Caution  

    You can impair the protection provided by the PCI-5124 if you use it in a manner not described in this document.

    Vertical

    Analog Input (Channel 0 and Channel 1)

    Number of Channels

    Two (simultaneously sampled)

    Connector

    BNC

    Impedance and Coupling

    Input impedance (software-selectable)

    50 Ω ± 2.0%

    1 MΩ ± 0.75% in parallel with a typical capacitance of 29 pF

    Input coupling (software-selectable)

    AC[1]

    DC

    GND

    Voltage Levels

    Table 1. Full Scale (FS) Input Range and Programmable Vertical Offset, 50 Ω Input
    Range (Vpk-pk) Vertical Offset Range
    0.2 V ±0.1 V
    0.4 V ±0.2 V
    1 V ±0.5 V
    2 V ±1 V
    4 V ±2 V
    10 V
    Table 2. FS Input Range and Programmable Vertical Offset, 1 MΩ Input
    Range (Vpk-pk) Vertical Offset Range
    0.2 V ±0.1 V
    0.4 V ±0.2 V
    1 V ±0.5 V
    2 V ±1 V
    4 V ±2 V
    10 V ±5 V
    20 V
    Maximum input overload

    50 Ω

    7 Vrms with |Peaks| ≤ 10 V

    1 MΩ

    |Peaks| ≤ 42 V

    Accuracy

    Resolution

    12 bits

    Table 3. DC Accuracy [2]
    Range (Vpk-pk) Accuracy
    0.2 V and 0.4 V ±(0.65% of input + 1.3 mV)
    1 V and 2 V ±(0.65% of input + 1.5 mV)
    4 V, 10 V, and 20 V[3] ±(0.65% of input + 10.0 mV)

    Programmable vertical offset accuracy

    ±0.4% of offset setting[4]

    Table 4. DC Drift
    Range (Vpk-pk) 50 Ω and 1 MΩ
    0.2 V, 0.4 V, 1 V, and 2 V ±(0.057% of input + 0.006% of FS + 100 μV) per °C
    4 V, 10 V, and 20 V[3] ±(0.057% of input + 0.006% of FS + 900 µV) per °C
    AC amplitude accuracy[4]

    50 Ω

    ±0.06 dB (±0.7%) at 50 kHz, typical

    1 MΩ

    ±0.09 dB (±1.0%) at 50 kHz, typical

    Crosstalk

    ≤-85 dB at 10 MHz, typical[5]

    Sparkle code rate[6]

    <300 ppt[7] with onboard clock or 200 MHz external clock, typical

    <3 ppt with 150 MHz external clock, typical

    0 with 100 MHz external clock, typical

    Bandwidth and Transient Response

    Table 5. Bandwidth (-3 dB) [8]
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V 85 MHz 75 MHz
    All other input ranges 150 MHz 145 MHz up to 40 °C[9]
    Table 6. Rise/Fall Time, Typical [8]
    Input Range (Vpk-pk) 50 Ω and 1 MΩ
    0.2 V 3.3 ns
    All other input ranges 2.4 ns
    Bandwidth limit filters[10]

    Noise filter

    20 MHz, typical

    2-pole Bessel filter

    Antialias filter

    60 MHz, typical

    4-pole elliptical filter

    AC coupling cutoff (-3 dB)[11]

    12 Hz

    Table 7. Passband Flatness, Typical [12]
    Filter Settings Input Range (Vpk-pk) 50 Ω and 1 MΩ
    Filters off 0.2 V
    • ±0.6 dB (DC to 20 MHz)
    • ±1.5 dB (20 MHz to 40 MHz)
    All input ranges except 0.2 V
    • ±0.5 dB (DC to 20 MHz)
    • ±1.0 dB (20 MHz to 50 MHz)
    • ±1.7 dB (50 MHz to 100 MHz)
    Antialias filter on All ranges -1.0 dB to +2.0 dB (DC to 55 MHz)
    Figure 1. PCI-5124 Frequency Response (Typical)

    Spectral Characteristics

    Table 8. Spurious-Free Dynamic Range with Harmonics (SFDR), Typical [13]
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V 75 dBc 70 dBc
    0.4 V 75 dBc 70 dBc
    1 V 72 dBc 70 dBc
    2 V 72 dBc 70 dBc
    4 V 65 dBc 67 dBc
    10 V 65 dBc 60 dBc
    20 V (1 MΩ only) 60 dBc
    Table 9. Total Harmonic Distortion (THD), Typical [14]
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V -74 dBc -68 dBc
    0.4 V -74 dBc -68 dBc
    1 V -72 dBc -68 dBc
    2 V -72 dBc -67 dBc
    4 V -63 dBc -66 dBc
    10 V -63 dBc -58 dBc
    20 V (1 MΩ only) -58 dBc

    Intermodulation distortion (Vpk-pk)[15]

    -75 dBc, typical

    Table 10. Signal-to-Noise Ratio (SNR), Typical [16]
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    Filters Off Antialias Filter On Filters Off Antialias Filter On
    0.2 V 57 dB 56 dB 53 dB 55 dB
    0.4 V 58 dB 57 dB 55 dB 57 dB
    1 V 58 dB 58 dB 57 dB 57 dB
    2 V 58 dB 58 dB 57 dB 57 dB
    4 V 56 dB 58 dB
    Table 11. Signal to Noise and Distortion (SINAD), Typical [17]
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    Filters Off Antialias Filter On Filters Off Antialias Filter On
    0.2 V 57 dB 56 dB 53 dB 55 dB
    0.4 V 58 dB 57 dB 55 dB 57 dB
    1 V 58 dB 58 dB 57 dB 57 dB
    2 V 58 dB 58 dB 57 dB 57 dB
    4 V 56 dB 57 dB
    Figure 2. PCI-5124 Dynamic Performance, 50 Ω, 1 V Input Range, 262,144-Point FFT, Typical
    Table 12. RMS Noise (Noise filter on; 50 Ω terminator connected to input)
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V 106 μVrms (0.053% FS) 116 μVrms (0.058% FS)
    0.4 V 188 μVrms (0.047% FS) 192 μVrms (0.048% FS)
    1 V 470 μVrms (0.047% FS) 480 μVrms (0.048% FS)
    2 V 940 μVrms (0.047% FS) 960 μVrms (0.048% FS)
    4 V 1.88 mVrms (0.047% FS) 1.92 mVrms (0.048% FS)
    10 V 4.7 mVrms (0.047% FS) 4.8 mVrms (0.048% FS)
    20 V (1 MΩ only) 9.4 mVrms (0.047% FS)
    Table 13. RMS Noise (Antialias filter on; 50 Ω terminator connected to input)
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V 126 μVrms (0.063% FS) 146 μVrms (0.073% FS)
    0.4 V 200 μVrms (0.05% FS) 216 μVrms (0.054% FS)
    1 V 500 μVrms (0.05% FS) 510 μVrms (0.051% FS)
    2 V 1.0 mVrms (0.05% FS) 1.02 mVrms (0.051% FS)
    4 V 2.04 mVrms (0.051% FS) 2.16 mVrms (0.054% FS)
    10 V 5.1 mVrms (0.051% FS) 5.2 mVrms (0.052% FS)
    20 V (1 MΩ only) 10.2 mVrms (0.051% FS)
    Table 14. RMS Noise (Filters off; 50 Ω terminator connected to input)
    Input Range (Vpk-pk) 50 Ω 1 MΩ
    0.2 V 128 μVrms (0.064% FS) 184 μVrms (0.092% FS)
    0.4 V 204 μVrms (0.051% FS) 264 μVrms (0.066% FS)
    1 V 510 μVrms (0.051% FS) 550 μVrms (0.055% FS)
    2 V 1.02 mVrms (0.051% FS) 1.08 mVrms (0.054% FS)
    4 V 2.08 mVrms (0.052% FS) 2.6 mVrms (0.065% FS)
    10 V 5.2 mVrms (0.052% FS) 5.5 mVrms (0.055% FS)
    20 V (1 MΩ only) 10.6 mVrms (0.053% FS)
    Figure 3. Representation of PCI-5124 Spectral Noise Density on 0.2 V Input Range, Noise Filter Enabled, 1 MΩ Input Impedance
    Figure 4. Representation of PCI-5124 Spectral Noise Density on 0.2 V Input Range, Full Bandwidth, 50 Ω Input Impedance

    Horizontal

    Sample Clock

    Sources

    Internal

    Onboard clock (internal VCXO)[18]

    External

    CLK IN (front panel SMB connector)

    Onboard Clock (Internal VCXO)

    Sample rate range

    Real-time sampling (single shot)

    3.052 kS/s to 200 MS/s[19]

    Random interleaved sampling (RIS)

    400 MS/s to 4 GS/s in multiples of 200 MS/s

    Phase noise density[20]

    <-100 dBc/Hz at 100 Hz, typical

    <-120 dBc/Hz at 1 kHz, typical

    <-130 dBc/Hz at 10 kHz, typical

    Sample clock jitter[21]

    ≤1 ps rms, typical (100 Hz to 100 kHz)

    ≤2 ps rms, typical (100 Hz to 1 MHz)

    Timebase frequency

    200 MHz

    Timebase accuracy

    Not phase-locked to Reference clock

    ±25 ppm

    Phase-locked to Reference clock

    Equal to the Reference clock accuracy

    Sample clock delay range

    ±1 Sample clock period

    Sample clock delay/adjustment resolution

    ≤5 ps

    External Sample Clock

    Sources

    CLK IN (front panel SMB connector)

    Frequency range[22]

    50 MHz to 210 MHz (CLK IN)

    Duty cycle tolerance

    45% to 55%

    Exported Reference clock destinations

    CLK OUT (front panel SMB connector)

    PFI<0..1> (front panel 9-pin mini-circular DIN connector)

    RTSI<0..7>

    Sample Clock Exporting

    Table 15. Exported Sample Clock Destinations
    Destination Maximum Frequency
    CLK OUT (front panel SMB connector) 210 MHz
    PXI_Trig<0..6>[23] 20 MHz
    PFI<0..1> (front panel 9-pin mini-circular DIN connector)[23] 25 MHz

    Phase-Locked Loop (PLL) Reference Clock

    Sources

    RTSI 7

    CLK IN (front panel SMB connector)

    Frequency range

    1 MHz to 20 MHz in 1 MHz increments[24]

    Duty cycle tolerance

    45% to 55%

    Exported Reference clock destinations

    CLK OUT (front panel SMB connector)

    PFI<0..1> (front panel 9-pin mini-circular DIN connector)

    RTSI<0..7>

    CLK IN (Sample Clock and Reference Clock Input, Front Panel Connector)

    Input voltage range

    Sine wave (Vpk-pk)

    0.65 V to 2.8 V (0 dBm to 13 dBm)

    Square wave (Vpk-pk)

    0.2 V to 2.8 V

    Maximum input overload

    7 Vrms with |Peaks| ≤ 10 V

    Impedance

    50 Ω

    Coupling

    AC

    CLK OUT (Sample Clock and Reference Clock Output, Front Panel Connector)

    Output impedance

    50 Ω

    Logic type

    3.3 V CMOS

    Maximum drive current

    ±48 mA

    Trigger

    Reference (Stop) Trigger

    spd-note-note
    Note  

    Refer to the following sections and the NI High-Speed Digitizers Help for more information about what sources are available for each trigger type.

    Trigger types

    Edge, window, hysteresis, video, digital, immediate, and software

    Trigger sources

    CH 0, CH 1, TRIG, RTSI <0..6>, and software

    Time resolution
    Time-to-digital conversion circuit (TDC) on

    Onboard clock

    50 ps

    External clock

    N/A

    TDC off

    Onboard clock

    5 ns

    External clock

    External clock period

    Minimum rearm time[25]

    TDC on

    10 µs

    TDC off

    2 µs

    Holdoff
    Onboard clock

    TDC on

    10 µs to 85.899 s

    TDC off

    2 µs to 85.899 s

    External clock (TDC off)

    200 × External Clock Period to (232 - 1) × External Clock Period

    Analog Trigger (Edge, Window, and Hysteresis Trigger Types)

    Sources

    CH 0 (front panel BNC connector)

    CH 1 (front panel BNC connector)

    TRIG (front panel BNC connector)

    Trigger level range

    CH 0, CH 1

    100% of FS

    TRIG (External Trigger)

    ±5 V

    Trigger level resolution

    10 bits (1 in 1,024)

    Edge trigger sensitivity

    CH 0, CH 1

    3.5% FS up to 50 MHz, increasing to 10% FS at 150 MHz

    TRIG (External Trigger, Vpk-pk)

    0.25 V up to 100 MHz, increasing to 1 V at 200 MHz

    Level accuracy

    CH 0, CH 1

    ±4.7% FS up to 10 MHz, typical

    TRIG (External Trigger)

    ±0.35 V up to 10 MHz, typical

    Trigger jitter

    ≤80 ps rms[26]

    Trigger filters

    Low-frequency (LF) reject

    50 kHz

    High-frequency (HF) reject

    50 kHz

    Digital Trigger (Digital Trigger Type)

    Sources

    RTSI<0..6>

    PFI<0..1> (front panel SMB connector)

    Video Trigger (Video Trigger Type)

    Sources

    CH 0 (front panel BNC connector)

    CH 1 (front panel BNC connector)

    TRIG (front panel BNC connector)

    Types

    Specific line

    Any line

    Specific field

    Standard

    Negative sync of NTSC, PAL, or SECAM signal

    TRIG (External Trigger, Front Panel Connector)

    Connector

    BNC

    Impedance

    1 MΩ in parallel with 22 pF

    Coupling

    AC

    DC

    AC-coupling cutoff (-3 dB)

    12 Hz

    Input voltage range

    ±5 V

    Maximum input overload

    |Peaks| ≤ 42 V

    PFI 0 and PFI 1 (Programmable Function Interface, AUX Front Panel Connectors)

    Connector

    9-pin mini-circular DIN

    Direction

    Bi-directional

    As an input (trigger)

    Destinations

    Start Trigger (Acquisition Arm)

    Reference (Stop) Trigger

    Arm Reference Trigger

    Advance Trigger

    Input impedance

    150 kΩ

    VIH

    2.0 V

    VIL

    0.8 V

    Maximum input overload

    -0.5 V to 5.5 V

    Maximum frequency

    25 MHz

    As an output (event)

    Sources

    Start Trigger (Acquisition Arm)

    Reference (Stop) Trigger

    End of Record

    Done (End of Acquisition)

    Probe Compensation[27]

    Output impedance

    50 Ω

    Logic type

    3.3 V CMOS

    Maximum drive current

    ±24 mA

    Maximum frequency

    25 MHz

    Waveform Specifications

    Onboard memory sizes

    8 MB per channel (4 MS per channel)

    32 MB per channel (16 MS per channel)

    256 MB per channel (128 MS per channel)

    Minimum record length

    1 sample

    Number of pretrigger samples

    Zero up to full record length[28]

    Number of posttrigger samples

    Zero up to full record length[28]

    Maximum number of records in onboard memory

    8 MB per channel

    21,845

    32 MB per channel

    87,381

    256 MB per channel

    100,000[29]

    Allocated onboard memory per record

    (Record Length × 2 bytes/S) + 200 bytes, rounded up to next multiple of 128 bytes

    or

    384 bytes, whichever is greater

    Calibration

    External Calibration

    External calibration calibrates the onboard references used in self-calibration and the external trigger levels. All calibration constants are stored in nonvolatile memory.

    Self-Calibration

    Self-calibration is done on software command. The calibration corrects for gain, offset, triggering, and timing errors for all input ranges.

    Calibration Specifications

    Interval for external calibration

    2 years

    Warm-up time

    15 minutes

    Dimensions and Weight

    Dimensions

    3U, one slot, PCI module

    35.5 cm x 2.0 cm x 11.3 cm

    (14.0 in. x 0.8 in. x 4.4 in.)

    Weight

    455 g (16 oz)

    Power

    +3.3 VDC

    1.3 A

    +5 VDC

    2.7 A

    +12 VDC

    130 mA

    -12 VDC

    0 A

    Total Power

    19.4 W

    Software

    Driver Software

    Driver support for this device was first available in NI-SCOPE 2.7.

    NI-SCOPE is an IVI-compliant driver that allows you to configure, control, and calibrate the PCI-5124. NI-SCOPE provides application programming interfaces for many development environments.

    Application Software

    NI-SCOPE provides programming interfaces, documentation, and examples for the following application development environments:

    • LabVIEW
    • LabWindows™/CVI™
    • Measurement Studio
    • Microsoft Visual C/C++

    Interactive Soft Front Panel and Configuration

    The NI-SCOPE Soft Front Panel (SFP) allows interactive control of the PCI-5124.

    The NI-SCOPE SFP is included on the NI-SCOPE media.

    NI Measurement Automation Explorer (MAX) also provides interactive configuration and test tools for the PCI-5124. MAX is included on the NI-SCOPE media.

    TClk Specifications

    You can use the NI TClk synchronization method and the NI-TClk driver to align the Sample clocks on any number of supported devices, in one or more chassis. For more information about TClk synchronization, refer to the NI-TClk Synchronization Help, which is located within the NI High-Speed Digitizers Help. For other configurations, including multichassis systems, contact NI Technical Support at ni.com/support.

    Intermodule SMC Synchronization Using NI-TClk for Identical Modules

    Specifications are valid under the following conditions:
    • All PXI-5124 modules installed in one NI PXI-1042 chassis.
    • All parameters set to identical values for each SMC-based module.
    • Sample clock set to 200 MS/s and all filters are disabled.
    spd-note-note
    Note  

    Although you can use NI-TClk to synchronize non-identical modules, these specifications apply only to synchronizing identical modules.

    Skew[30]

    500 ps, typical

    Average skew after manual adjustment[31]

    <10 ps, typical

    Sample clock delay/adjustment resolution

    ≤5 ps, typical

    Environment

    Maximum altitude

    2,000 m (at 25 °C ambient temperature)

    Pollution Degree

    2

    Indoor use only.

    Operating Environment

    Ambient temperature range

    0 °C to 45 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    10% to 90%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Storage Environment

    Ambient temperature range

    -40 °C to 71 °C (Tested in accordance with IEC 60068-2-1 and IEC 60068-2-2.)

    Relative humidity range

    5% to 95%, noncondensing (Tested in accordance with IEC 60068-2-56.)

    Compliance and Certifications

    Safety

    This product is designed to meet the requirements of the following electrical equipment safety standards for measurement, control, and laboratory use:

    • IEC 61010-1, EN 61010-1
    • UL 61010-1, CSA 61010-1
    spd-note-note
    Note  

    For UL and other safety certifications, refer to the product label or the Online Product Certification section.

    Electromagnetic Compatibility

    This product meets the requirements of the following EMC standards for electrical equipment for measurement, control, and laboratory use:
    • EN 61326-1 (IEC 61326-1): Class A emissions; Basic immunity
    • EN 55011 (CISPR 11): Group 1, Class A emissions
    • EN 55022 (CISPR 22): Class A emissions
    • EN 55024 (CISPR 24): Immunity
    • AS/NZS CISPR 11: Group 1, Class A emissions
    • AS/NZS CISPR 22: Class A emissions
    • FCC 47 CFR Part 15B: Class A emissions
    • ICES-001: Class A emissions
    spd-note-note
    Note  

    In the United States (per FCC 47 CFR), Class A equipment is intended for use in commercial, light-industrial, and heavy-industrial locations. In Europe, Canada, Australia, and New Zealand (per CISPR 11), Class A equipment is intended for use only in heavy-industrial locations.

    spd-note-note
    Note  

    Group 1 equipment (per CISPR 11) is any industrial, scientific, or medical equipment that does not intentionally generate radio frequency energy for the treatment of material or inspection/analysis purposes.

    spd-note-note
    Note  

    For EMC declarations, certifications, and additional information, refer to the Online Product Certification section.

    CE Compliance

    This product meets the essential requirements of applicable European Directives, as follows:

    • 2014/35/EU; Low-Voltage Directive (safety)
    • 2014/30/EU; Electromagnetic Compatibility Directive (EMC)

    Online Product Certification

    Refer to the product Declaration of Conformity (DoC) for additional regulatory compliance information. To obtain product certifications and the DoC for this product, visit ni.com/certification, search by model number or product line, and click the appropriate link in the Certification column.

    Environmental Management

    NI is committed to designing and manufacturing products in an environmentally responsible manner. NI recognizes that eliminating certain hazardous substances from our products is beneficial to the environment and to NI customers.

    For additional environmental information, refer to the Minimize Our Environmental Impact web page at ni.com/environment. This page contains the environmental regulations and directives with which NI complies, as well as other environmental information not included in this document.

    Waste Electrical and Electronic Equipment (WEEE)

    spd-note-weee
    EU Customers  

    At the end of the product life cycle, all NI products must be disposed of according to local laws and regulations. For more information about how to recycle NI products in your region, visit ni.com/environment/weee.

    电子信息产品污染控制管理办法(中国RoHS)

    spd-note-china-rohs
    中国客户  

    National Instruments符合中国电子信息产品中限制使用某些有害物质指令(RoHS)。关于National Instruments中国RoHS合规性信息,请登录 ni.com/environment/rohs_china。(For information about China RoHS compliance, go to ni.com/environment/rohs_china.)

    • 1 AC coupling available on 1 MΩ input only.
    • 2 Programmable vertical offset = 0 V. Within ±5 °C of self-calibration temperature.
    • 3 1 MΩ input only.
    • 4 Within ±5 °C of self-calibration temperature.
    • 5 CH 0 to/from CH 1, External Trigger to CH 0 or CH 1.
    • 6 Results based on 2×1012 samples.
    • 7 ppt = parts per trillion (1012).
    • 8 Filters off.
    • 9 135 MHz above 40 °C.
    • 10 Only one filter can be enabled at any given time. The antialias filter is enabled by default.
    • 11 AC coupling available on 1 MΩ path only.
    • 12 Referenced to 50 kHz.
    • 13 Filters off or antialias filter on. 10 MHz, -1 dBFS input signal. Includes the 2nd through the 5th harmonics. Measured from 5 kHz to 100 MHz.
    • 14 Filters off or antialias filter on. 10 MHz, -1 dBFS input signal. Includes the 2nd through the 5th harmonics.
    • 15 0.2 V to 2.0 V input ranges on 50 Ω input. Filters off or antialias filter on. Two tones at 10.2 MHz and 11.2 MHz. Each tone is -7 dBFS.
    • 16 Excludes harmonics. 10 MHz, -1 dBFS input signal. Measured from DC to 100 MHz.
    • 17 Includes harmonics. 10 MHz, -1 dBFS input signal. Measured from DC to 100 MHz.
    • 18 Internal Sample clock is locked to the Reference clock or derived from the onboard VCXO.
    • 19 Divide by n decimation used for all rates less that 200 MS/s.
    • 20 10 MHz input signal.
    • 21 Includes the effects of the converter aperture uncertainty and the clock circuitry jitter. Excludes trigger jitter.
    • 22 Divide by n decimation available where 1 ≤ n ≤ 65,535.
    • 23 Decimated Sample clock only.
    • 24 Default of 10 MHz. The PLL Reference clock frequency must be accurate to ±50 ppm.
    • 25 Holdoff set to 0. Onboard Sample clock at maximum rate.
    • 26 Within ±5 °C of self-calibration temperature.
    • 27 1 kHz, 50% duty cycle square wave, PFI 1 only.
    • 28 Single-record mode and multiple-record mode.
    • 29 It is possible to exceed these numbers if you fetch records while acquiring data.
    • 30 Caused by clock and analog path delay differences. No manual adjustment performed.
    • 31 For information about manual adjustment, refer to the Synchronization Repeatability Optimization topic in the NI-TClk Synchronization Help available at ni.com/manuals. For additional help with the adjustment process, contact NI Technical Support at ni.com/support.

    Recently Viewed Topics