Table Of Contents

Defining NI-Sync Clock Terminals

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    Last Modified: September 15, 2017

    Using niSync Connect Clock Terminals, you can route clocks between chassis, discipline the PXI backplane clock to the oscillator of a system timing module, or route an external time reference throughout a chassis or to multiple chassis. The function uses clock terminals to route clock signals between devices. The following terminals are available with NI-Sync:

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    Note  

    Not all of the following terminals are available on every PXI or PXIe chassis. Refer to the hardware documentation to determine if your device supports a particular source or destination terminal.

    Clock Source Terminals

    Clock Source Description
    ClkIn The ClkIn input connector on the front panel of the device. Using ClkIn, you can connect a 10 MHz reference clock directly to the PXI_Clk10_In pin. You also can phase lock a clock connected to ClkIn using a PLL circuit, or you can use a clock connected to ClkIn as the synchronization clock for the front and rear zones of your chassis.
    PXI_Clk10 The 10 MHz backplane clock of the PXI or PXIe chassis.
    Oscillator The oscillator of the device specified in the instrument handle terminal.
    DDS Clock The DDS signal generated by the device specified in the instrument handle terminal.
    PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of your device. PFI LVDS lines consist of paired PFI lines. You can use PFI_LVDS to route clock and trigger signals between multiple PXI chassis at high speeds. You can achieve faster speeds when using an LVDS line compared to a single-ended PFI line. Signals on PFI LVDS lines use the standard PFI synchronization clock.
    PXIe_DStarC<n> The differential star trigger line of your PXIe chassis. Use DStarC lines to route clock and/or trigger signals from a peripheral slot to a system timing slot.
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    Note  

    Each PXIe_DStarC trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis documentation for more information on the mapping of differential star trigger lines.

    PXIe_DStarA The differential star trigger line of your PXIe chassis. Use DStarA lines to route clock signals from a system timing slot to a peripheral slot.
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    Note  

    Each PXIe_DStarA trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis documentation for more information on the mapping of differential star trigger lines.

    Clock Destination Terminals

    Clock Destination Description
    PXI_Clk10_In The connector pin that you use to provide the backplane with a reference 10 MHz signal from the system timing slot. When you connect a signal to this pin, PXI_Clk10 and PXIe_Clk100 are phase aligned to this reference.
    ClkOut The ClkOut connector on the front panel of the device. Use this terminal to export clocks to an external device or to another chassis. You can export only clock signals through the ClkOut connector.
    BoardClk The timekeeper used to schedule future time events and timestamping on PXI-6682, PXI-6682H, PXI-6683, and PXI-6683H modules. BoardClk accepts a 10 MHz reference clock and multiplies it by 10 to create a 100 MHz clock for use as a timekeeper. The only two valid sources for BoardClk are the on-board oscillator and PXI_Clk10. You can specify the source of BoardClk using niSync Connect Clock Terminals.
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    Note  

    BoardClk is a valid terminal only on PXI-668x devices.

    PFI_LVDS<n> The PFI_LVDS output connector on the front panel of your device.
    PXIe_DStarA<n> The differential star trigger line of the PXIe chassis. Use DStarA lines to route clock signals from the system timing slot to a peripheral slot of the chassis.

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