Table Of Contents

Setting and Dividing a Synchronization Clock

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    Last Modified: September 15, 2017

    The following steps will set and divide the synchronization clock of the front and rear zones of a PXI or PXIe chassis:

    1. Place Initialize on the diagram.
    2. Place niSync Properties on the diagram and select Synchronization Clock Properties»Synchronization Clock Source (PFI, PFI_LVDS) as the first property.
    3. Right-click the Synchronization Clock Source (PFI, PFI_LVDS) property and select Change to Write.
    4. Wire a control or constant to the Synchronization Clock Source (PFI, PFI_LVDS) property. The value you select here becomes the synchronization clock for the front zone of the PXI chassis, which comprises the front panel inputs and outputs of each module. The default is PXI_CLK10.
    5. Add another parameter to niSync Properties and select Synchronization Clock Properties»Synchronization Clock Source (PXI_Trig, PXI_Star, PXIe_DStarB).
    6. Wire a control or constant to the Synchronization Clock Source (PXI_Trig, PXI_Star, PXIe_DStarB) property. The value you select here becomes the synchronization clock for the back zone of the PXI chassis, which includes all the chassis' backplane trigger lines. The default is PXI_CLK10.
    7. Add another parameter to niSync Properties and select Synchronization Clock Properties»Clock Divisor 1 as the third property.
      spd-note-note
      Note  

      Clock Divisor properties apply to whatever synchronization clock source is placed in the same niSync Properties function. This example sets a clock divisor for both the front and rear zone synchronization clocks, but if niSync Properties only contained Synchronization Clock Source (PFI, PFI_LVDS), the Clock Divisor properties would only divide the synchronization clock for the front zone.

    8. (Optional) Add a fourth parameter to niSync Properties and select Synchronization Clock Properties»Clock Divisor 2 to use a second value to divide the synchronization clock.
    9. Wire a control or a constant to the Clock Divisor 1 and/or Clock Divisor 2 parameters and set the number(s) you would like to divide the clock by.
      spd-note-note
      Note  

      Values for the Clock Divisor 1 and Clock Divisor 2 properties must be a power of 2, up to 512.

      You have successfully set the synchronization clock source for both the front and rear zones of the chassis. You have also created two divided synchronization clocks using the values you set for the Clock Divisor 1 and Clock Divisor 2 properties.
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