Table Of Contents

Routing and Locking to the PLL Reference Clock

Version:
    Last Modified: September 15, 2017

    Routes the external reference clock from ClkIn to the PXI_Clk10_In connector and waits until the system is phase-locked.

    Enabling and Configuring a Phase-Locked Loop
    1. Place Connect Clock Terminals on the diagram.
    2. Select ClkIn as the source terminal and select PXI_Clk10_In as the destination terminal.
    3. Place a While Loop on the diagram. Adding a While Loop ensures that the system is phase-locked before moving on.
    4. Place niSync Properties inside the While Loop.
    5. Select Clk Properties»PLL Locked? as the first parameter of niSync Properties.
    6. Wire PLL Locked? to the conditional terminal of the While Loop to stop the loop once the system is phase-locked.
      1. (Optional) Wire an indicator to the PLL Locked? parameter to display PLL lock status on the front panel.
    7. (Optional) Add a Wait function inside the While Loop to delay iterations of the loop. Using the Wait function eases the load on the processor.
    8. Place Disconnect Clock Terminals on the block diagram outside the While Loop and wire source terminal and destination terminal to close the clock route between ClkIn and PXI_Clk10_In.
    9. Place Close on the diagram to terminate the NI-Sync session.
    This program disconnects the clock at ClkIn right after the PLL circuit is locked. To maintain the phase lock throughout a program, place your code outside the While Loop and before Disconnect Clock Terminals. You can now use the phase-locked backplane clock to synchronize modules within the chassis or export it for multi-chassis synchronization.

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