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Routing a Synchronization Clock Along a Trigger Line

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    Last Modified: September 15, 2017

    You can route full-speed or divided synchronization clocks through trigger lines using NI-Sync. With this technique, you can export a DDS clock using a PFI line and send full-speed or divided clocks along routes that are not accessible when you use clock terminals alone.

    Setting and Dividing a Synchronization Clock
    1. Place Connect Trigger Terminals on the diagram.
    2. Wire a constant or control to source terminal and destination terminal.
    3. Select Synchronization Clock (Divided 2) for source terminal. This divides the synchronization clock by the value you set in the Clock Divisor 2 property of niSync Properties and uses the result as the source for this trigger. You can also select Synchronization Clock (Divided 1) or Synchronization Clock (Full Speed).
    4. Select a destination terminal for Connect Trigger Terminals:
      spd-note-caution
      Caution  

      Routing a clock signal through a PXI_Trig line is not recommended. due to poor clock signal integrity caused by the topology of the PXI_Trig lines. Use PXI_Star, PXIe_DStar, or PFI lines instead.

      • Select a PXI_Star line to route the specified clock through the backplane trigger lines of the chassis.
      • Select a front panel terminal (PFI, PFI_LVDS) to route the specified clock through the front zone of the chassis to another PXI chassis, a physically connected module in the same chassis, or an external device.
      • Select PXIe_DStarB to route the specified clock from a system timing module to a peripheral slot.
      • Select PXIe_DStarC to route the specified clock from a peripheral slot to a system timing module.
    5. Place Disconnect Trigger Terminals on the diagram to free the trigger lines for other applications.
    6. Place Close on the diagram to end the NI-Sync session. The synchronization clock you set using niSync Properties is routed to a different location in the chassis using a trigger line.

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