Table Of Contents

Connect Trigger Terminals (G Dataflow)

Version:
Last Modified: March 15, 2017

Routes triggers through the PXI backplane, between devices, or between multiple chassis.

Once a terminal route is connected, you can invert the trigger signal at the destination terminal, synchronize the trigger to the rising or falling edge of a synchronization clock, fire the trigger asynchronously, or route the trigger to other trigger terminals.

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Note  

The destination terminal determines the source of the trigger's synchronization clock. PFI and PFI_LVDS lines are in the front trigger zone, and PXI_Trig, PXI_Star, and PXIe_DStar lines are in the rear trigger zone. You can select the source of the full speed synchronization clock for a given trigger zone and adjust the speed of the divided clocks by using niSync Properties.

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update edge

The synchronization clock update edge on which the connected signal is propagated.

The source and destination terminals must be connected synchronously for this parameter to apply.

Name Value Description
Rising Edge 0 Propagates the trigger when the digital signal of the synchronization clock transitions from low to high, i.e. the rising edge.
Falling Edge 1 Propagates the trigger when the digital signal of the synchronization clock transitions from high to low, i.e. the falling edge.

Default: Rising Edge

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synchronization clock

A string value that specifies whether to use the full-speed or a divided synchronization clock to control trigger firing.

The trigger is synchronized with the rising or falling edge of the clock you select in this parameter.

Name Value Description
Asynchronous SyncClkAsync The trigger is not synchronized to any clock.
Full Speed Clock SyncClkFullSpeed Uses the full speed frequency of the synchronization clock to synchronize the trigger.
Divided Clock 1 SyncClkDivided1 Divides the synchronization clock by the value specified in the Clock Divisor 1 property of niSync Properties and uses the frequency of the divided clock to synchronize the trigger.
Clock Divisor 2 SyncClkDivided2 Divides the synchronization clock by the value specified in the Clock Divisor 2 property of niSync Properties and uses the frequency of the divided clock to synchronize the trigger.
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instrument handle in

The instrument handle that you obtain from Initialize.

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error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Default: No error

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source terminal

The source trigger terminal to connect to the destination terminal.

Name Description
PXI_Trig<n> The basic trigger lines of a PXI or PXIe chassis.
PXI_Star<n> The star trigger lines of a PXI or PXIe chassis.
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Note  

Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis.

PFI<n> The PFI connectors on the front panel of the module. You can use PFI connectors to route triggers between multiple chassis or devices.
PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of your device. Signals on PFI LVDS lines use the standard PFI synchronization clock.
Ground The Ground connector continuously outputs a logic low signal, unless it is inverted.
Full Speed Clock The full speed synchronization clock signal of the destination terminal zone. Use this source to send a full-speed clock signal along a trigger line (for example, to route a PXI_Clk10 clock signal to a PFI line).
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Caution  

Routing a clock signal through a PXI_Trig line is not recommended, due to poor clock signal integrity caused by the topology of the PXI_Trig lines. Use PXI_Star, PXIe_DStar, or PFI lines instead.

Divided Clock 1 The first divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 1 parameter of niSync Properties and uses the result as the trigger source.
Divided Clock 2 The second divided clock signal of the destination terminal zone. This source divides the synchronization clock of the destination terminal by the value you specify in the Clock Divisor 2 property of niSync Properties and uses the result as the trigger source.
ClkIn The ClkIn connector on the front panel of the device. Use this terminal to route triggers from an external device.
PXIe_DStarC<n> The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis.
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Note  

Each PXIe_DStarC trigger is mapped to a single slot. This mapping is vendor specific. Refer to your chassis documentation to determine the orientation of differential star trigger lines.

PXIe_DStarB The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis.
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destination terminal

The destination trigger terminal to which the source terminal connects.

Name Description
PXI_Trig<n> The basic trigger lines of the PXI or PXIe chassis.
PXI_Star<n> The star trigger lines of the PXI or PXIe chassis. Each star trigger line is a dedicated connection between the system timing slot and one other slot.
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Note  

Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis.

PFI<n> The PFI connectors on the front panel of the module.
PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the module.
PXIe_DStarB<n> The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis.
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Note  

Each PXIe_DStarB trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis documentation to determine the orientation of differential star trigger lines.

PXIe_DStarC The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis.
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invert

A ring value that specifies whether or not to invert the source terminal signal at the destination terminal.

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Note  

The source and destination must be connected synchronously for the signal to be inverted.

Name Value Description
Don't Invert Signal 0 Keeps the digital signal of the source trigger terminal in its original format.
Invert Signal 1 Inverts the digital signal of the source trigger terminal so that its rising edges are now its falling edges, and vice versa.

Default: Don't Invert Signal

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instrument handle out

The session handle that you obtain from Initialize.

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error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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