Table Of Contents

Connect Software Trigger (G Dataflow)

Version:
Last Modified: March 15, 2017

Connects the global software trigger terminal to a destination trigger terminal.

Once you connect the global software trigger, you can fire the trigger using Send Software Trigger.

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Note  

The destination terminal you specify in this function determines the full-speed synchronization clock used by the global software trigger. PFI and PFI_LVDS lines are in the front trigger zone, and PXI_Trig, PXI_Star, and PXIe_DStarB lines are in the rear trigger zone. You can select the source of the synchronization clock for a given trigger zone and adjust the speed of the divided clocks with niSync Properties.

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update edge

The synchronization clock update edge on which the connected signal is propagated.

The source and destination terminals must be connected synchronously for this parameter to apply.

Name Value Description
Rising Edge 0 Propagates the trigger when the digital signal of the synchronization clock transitions from low to high, i.e. the rising edge.
Falling Edge 1 Propagates the trigger when the digital signal of the synchronization clock transitions from high to low, i.e. the falling edge.

Default: Rising Edge

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synchronization clock

The clock to use to synchronize a trigger signal.

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Note  

Asynchronous connections are not valid for software trigger terminal connections.

Name Description
Full Speed Clock Uses the full speed frequency of the synchronization clock to synchronize the trigger.
Divided Clock 1 Divides the synchronization clock by the value specified in the Clock Divisor 1 property of the niSync Property Node and uses the frequency of the divided clock to synchronize the trigger.
Divided Clock 2 Divides the synchronization clock by the value specified in the Clock Divisor 2 property of the niSync Property Node and uses the frequency of the divided clock to synchronize the trigger.

Default: Full Speed Clock

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instrument handle in

The instrument handle that you obtain from Initialize.

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error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Default: No error

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source terminal

The source software trigger terminal to connect to the destination terminal.

The only acceptable value is Global Software Trigger.

Default: Global Software Trigger

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destination terminal

The destination trigger terminal that the global software trigger terminal will connect to.

Name Description
PXI_Trig<n> The basic trigger lines of a PXI or PXIe chassis.
PXI_Star<n> The star trigger lines of a PXI or PXIe chassis. Each star trigger line is a dedicated connection between the system timing slot and one other slot.
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Note  

Each PXI_Star trigger is mapped to a single slot. This mapping is vendor specific. Refer to the hardware documentation to determine the orientation of PXI_Star lines in the chassis.

PFI<n> The PFI connectors on the front panel of the module.
PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the device.
PXIe_DStarB<n> The differential star trigger lines of the PXIe chassis. Use PXIe_DStarB lines to send trigger signals from the system timing slot to a peripheral slot of the chassis.
PXIe_DStarC The differential star trigger lines of the PXIe chassis. Use PXIe_DStarC lines to send trigger and clock signals from a peripheral slot to the system timing slot of the chassis.

Default: PXI_Trig0

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invert

A ring value that specifies whether or not to invert the source terminal signal at the destination terminal.

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Note  

The source and destination must be connected synchronously for the signal to be inverted.

Name Value Description
Don't Invert Signal 0 Keeps the digital signal of the source trigger terminal in its original format.
Invert Signal 1 Inverts the digital signal of the source trigger terminal so that its rising edges are now its falling edges, and vice versa.

Default: Don't Invert Signal

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delay

The number of seconds to delay the global software trigger pulse.

The delay must be a multiple of the synchronization clock period. The global software trigger can be delayed up to 15 clock cycles for each route.

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Note  

This input is not supported on the NI PXIe-6674 or the NI PXIe-6674T.

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instrument handle out

The instrument handle that you obtain from Initialize.

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error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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