Table Of Contents

Connect Clock Terminals (G Dataflow)

Version:
Last Modified: March 15, 2017

Connects a source clock terminal to a destination clock terminal.

A clock terminal connection is characterized by its source terminal and destination terminal.

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instrument handle in

The instrument handle that you obtain from Initialize.

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error in

Error conditions that occur before this node runs.

The node responds to this input according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Default: No error

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source terminal

The source clock terminal of the clock you would like to connect.

Name Description
PXI_Clk10 The 10 MHz backplane clock of the PXI or PXIe chassis.
ClkIn The ClkIn input connector on the front panel of your device.
Oscillator The oscillator of the device specified in the instrument handle terminal.
DDS Clock The DDS signal generated by the device specified in the instrument handle terminal.
PFI_LVDS<n> The PFI low voltage differential signaling (LVDS) input/output connectors on the front panel of the module.
PXIe_DStarC<n> The differential star trigger line of the PXIe chassis. Use DStarC lines to route clock and/or trigger signals from a peripheral slot to a system timing slot.
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Note  

Each PXIe_DStarC trigger is mapped to a single slot. This mapping is vendor-specific. Refer to the chassis' documentation for more information on the mapping of differential star trigger lines.

PXIe_DStarA The differential star trigger line of the PXIe chassis. Use DStarA lines to route clock signals from a system timing slot to a peripheral slot.
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Note  

Each PXIe_DStarA trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis' documentation for more information on the mapping of differential star trigger lines.

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destination terminal

The destination clock terminal to which the source terminal connects.

Name Description
PXI_Clk10_In The connector pin used to provide the backplane with a reference 10 MHz signal from the system timing slot. When you connect a signal to this pin, PXI_Clk10 and PXIe_Clk100 are phase-aligned to this reference.
ClkOut The ClkOut connector on the front panel of the module.
BoardClk The timekeeper used to schedule future time events and timestamping on certain modules. BoardClk accepts a 10 MHz reference clock and multiples it by 10 to create a 100 MHz clock for use as a timekeeper.
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Note  

BoardClk is a valid terminal only on PXI-668x devices.

PFI_LVDS<n> The PFI_LVDS output connector on the front panel of your device.
PXIe_DStarA<n> The differential star trigger line of the PXIe chassis. Use DStarA lines to route clock signals from a system timing slot to a peripheral slot.
spd-note-note
Note  

Each PXIe_DStarA trigger is mapped to a single slot. This mapping is vendor specific. Refer to the chassis' documentation for more information on the mapping of differential star triger lines.

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instrument handle out

The session handle that you obtain from Initialize.

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error out

Error information.

The node produces this output according to standard error behavior.

Standard Error Behavior

Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

error in does not contain an error error in contains an error
If no error occurred before the node runs, the node begins execution normally.

If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

Where This Node Can Run:

Desktop OS: Windows

FPGA: Not supported


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