Table Of Contents

Using Scan Interface Mode with Individual Modules

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    Last Modified: October 11, 2017

    You may be able to use the Scan Interface for supported individual modules even if the chassis you are using is in FPGA Interface programming mode or does not support Scan Interface programming mode. First you must let LabVIEW discover the modules in the chassis and download a compiled bitfile to the chassis. Using modules that require the high-speed interface, such as the NI 951x, may also require a downloaded compiled bitfile. You must have the LabVIEW FPGA module installed to compile bitfiles for the FPGA.

    After setting up your project, discovering modules, and downloading the bitfile to the chassis, you can use modules under the FPGA target in FPGA Interface programming mode and use modules under the Real-Time Scan Resources item in Scan Interface programming mode.

    If you have both the LabVIEW Real-Time Module and the LabVIEW FPGA Module installed, you can create user-defined I/O variables to transfer custom I/O data between FPGA VIs and RT VIs. You can also synchronize the execution of code in FPGA VIs and RT VIs.

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    Note  

    If the chassis is in FPGA Interface programming mode, you must always use the Open FPGA VI Reference function to download a compiled bitfile to the FPGA before using modules that are under the Real-Time Scan Resources item. You must ensure that the bitfile is running on the FPGA before accessing those modules.

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    Tip  

    There is a short delay between the time when the Open FPGA VI Reference function finishes running and the time when user-defined variables and modules under the Real-Time Scan Resources item return valid data. If you have user-defined variables in your VI, run the Open FPGA VI Reference function and then read the variables in a loop until they return no errors.

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    Note  

    If the chassis is in FPGA Interface programming mode, using the Scan Interface reserves two of the available DMA FIFOs and occupies a portion of the FPGA space, resulting in a longer compile time than that for a bitfile with no modules in Scan Interface programming mode.

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    Note  

    If any modules are under the Real-Time Scan Resources item, you cannot write to the Sleep channel of the FPGA target.

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    Note  

    The FPGA VI in the example procedure contains no FPGA code. The only purpose of this FPGA VI is to download to a module bitfile to the chassis. The module bitfile specifies the types and slot locations of all modules in the chassis. If you have LabVIEW FPGA code to execute in your application, you include it in the FPGA VI. When you compile and run the RT VI, it downloads the module bitfile and all FPGA code to the chassis.

    1. Create the LabVIEW project.
      1. Configure the system.
      2. Drag and drop the C Series module(s) that will run in Scan Interface mode under the Real-Time Scan Resources item. Leave any modules you plan to write FPGA code for under the FPGA target.
    2. Download the bitfile.
      1. Create a new VI under the FPGA target and save it with your project files. You will use this FPGA VI from an RT VI to download the module bitfile to the chassis.
      2. Right-click the FPGA VI and select Create Build Specification from the shortcut menu. Under Build Specifications, right-click the new build specification for the example FPGA VI, select Build, and wait for the build to complete.
      3. Create a new VI under the RT target and save it with your Project files.
      4. Add an Open FPGA VI Reference function to the block diagram of the new RT VI.
      5. Right-click the Open FPGA VI Reference function and select Configure Open FPGA VI Reference from the shortcut menu to open the Configure Open FPGA VI Reference dialog box.
      6. Select the FPGA VI you created in step 1, make sure that the Run the FPGA VI checkbox is enabled, and click OK to close the dialog box.
      7. Place the code you want to run in the RT VI on the block diagram to the right of the Open FPGA VI Reference function.
      8. Enclose the code in a structure such as a Timed Loop or While Loop.
      9. Add a Close FPGA VI Reference function to the block diagram to the right of the structure enclosing the code.
      10. Connect the Open FPGA VI Reference function to the Close FPGA VI Reference function through the structure that encloses the code.
      11. Run the RT VI.

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