Table Of Contents

Bus Settings (Logic Analyzer)

Version:
    Last Modified: May 14, 2018

    You can use the Buses tab to add, remove, and configure buses for the Logic Analyzer. Access the Buses tab by clicking the icon in the Logic Analyzer section and selecting Buses.

    The following configuration options are available when Mode is Custom. The Custom mode allows you to analyze a customized set of data lines.

    Setting Description
    Status Enables or disables signal acquisition on the bus lines.
    Name Bus name.
    Mode Bus mode.
    Bus lines Data lines.
    Clock This setting is reserved for future use. Selecting a data line for Clock or Enable adds that line to the display, but the setting does not affect the signal acquisition in any way.
    Enable This setting is reserved for future use. Selecting a data line for Clock or Enable adds that line to the display, but the setting does not affect the signal acquisition in any way.
    Clock active This setting is reserved for future use.
    Enable active This setting is reserved for future use.
    Endianness This setting is reserved for future use.

    The following configuration options are available when Mode is I2C:

    Setting Description
    Status Enables or disables signal acquisition on the bus lines.
    Name Bus name.
    Mode Bus mode.
    Format Display format of the interpreted data.
    Clock (SCL) Clock signal.
    Data (SDA) Data signal.

    The following configuration options are available when Mode is SPI:

    Setting Description
    Status Enables or disables signal acquisition on the bus lines.
    Name Bus name.
    Mode Bus mode.
    Format Display format of the interpreted data.
    MOSI Master output, slave input line.
    MISO Master input, slave output line.
    SCLK Serial clock line.
    SS Slave select line.
    Bits per transfer Number of bits in one transmission word.
    Bit order Determines the bit order during data interpretation.
    Clock polarity (CPOL) Determines the idle state of the clock line.
    Clock phase(CPHA) Determines whether the data line is sampled on the leading or tailing edge of the clock line.
    SS active Determines whether the data is sampled when the SS line is high or low.

    The following configuration options are available when Mode is UART:

    Setting Description
    Status Enables or disables signal acquisition on the bus lines.
    Name Bus name.
    Mode Bus mode.
    Format Display format of the interpreted data.
    Data Data line.
    Bits per transfer Number of bits in one transmission word.
    Polarity Determines whether to invert the bits that the Logic Analyzer reads from the data line.
    Parity Type of the parity bit. Select None if no parity bit is used.
    Baud rate Sampling rate of the Logic Analyzer.
    Stop bits Number of the stop bits in the data line.

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