The NI ELVIS III provides eight differential (or 16 single-ended) high-impedance analog input channels on the NI ELVIS III Prototyping Board. These inputs are divided into two identical banks (Bank A and Bank B) to enable simultaneous processing in the FPGA. Each of the banks consists of a channel multiplexer (MUX), mode selector, gain selector, conditioning circuit, and ADC. For applications that use multiple channels, each of the selected channels are scanned into the ADC using the MUX.
There is one channel multiplexer (MUX) in each of the analog input banks. Its function is to select the active channel(s) where the analog signal is channeled through the analog input circuitry and eventually to the ADC. The MUX in bank A will select the channels from Bank A/AI0 to A/AI7 while MUX in bank B will select the channels from Bank B/AI0 to B/AI7.
The mode selector selects between differential or single-ended input modes. In differential mode, the analog input channel selected is referenced to its associated pair while in single-ended mode, the analog input channel selected is referenced to the analog ground (AGND). Refer to the Connecting Analog Input Signals section for more information.
The gain selector enables the user to select the input range of ±10 V, ±5 V, ±2 V, and ±1 V for the analog input operation. It is important to select a suitable input range that is larger but close to the peak-to-peak amplitude of the analog signal to be measured. This ensures that the maximum resolution of the ADC is utilized for better readout accuracy. The NI ELVIS III can sample channels in any order of the input range at the maximum conversion rate or lower. Each channel in a scan list can be individually programmed with a different input range.
The conditioning circuit receives the analog signal from the gain selector stage and it shapes the analog signal using its internal circuitry so that the analog signal can be read by the ADC correctly.
The NI ELVIS III uses an analog-to-digital converter (ADC) to convert the AI signal into a 16-bit digital number.
The FPGA processes the digital number which represents the analog signal read by analog input circuitry. The NI ELVIS III can perform both single and multiple analog to digital conversions for a fixed or infinite number of samples. The first-in-first-out buffer inside the FPGA can be implemented to hold the digital numbers during analog input acquisitions to ensure no data is lost.