Table Of Contents

cRIO-904x Considerations

Version:
    Last Modified: November 16, 2017

    This section contains information on using the cRIO-9040, 9041, 9042, 9043, 9044, 9045, 9046, 9047, 9048, and 9049 with NI-DAQmx.

    Slot Program Mode

    In MAX, when you add a C Series module to a CompactRIO controller there are three program modes to choose from.

    • Real-Time (NI-DAQmx)
    • Real-Time Scan
    • LabVIEW FPGA

    In order for DAQmx to communicate with the module, the module must be in Real-Time (NI-DAQmx) mode.

    spd-note-note
    Note  

    Not all modules support Real-Time (NI-DAQmx).

    Hardware Timed Single Point Sample Mode

    The cRIO-904x controller supports hardware timed single point (HWTSP) sample mode with a few caveats.

    • The NI 9260 does not support HWTSP.
    • The NI 9361 does not support HWTSP.
    • C Series Scanned Devices do not default to the lowest latency mode. They default to a slower convert rate to allow more time for settling. This behavior limits the maximum HWTSP acquisition rate of the module to allow more time for settling. If you prefer, you can configure the module for a faster acquisition rate with less time for settling. For additional information, see Sampling Rate Considerations.

    Model Names

    CompactRIO may use slightly different C Series model names and product IDs compared to CompactDAQ. For CompactRIO, see C Series Module IDs on ni.com.

    Time-Based Features for Network-Synchronized Devices

    cRIO-904x chassis features automatic network-based synchronization with compatible networks and NI Linux RT controllers.

    Timing Considerations

    CompactRIO controllers handle sampling rate and the default value for the hardware-timed mode differently than CompactDAQ chassis.

    In a cRIO-9040, 9041, 9042, 9043, 9044, 9045, 9046, 9047, 9048, and 9049 controller with C Series Slow Sample devices, such as the NI 9211, if the sampling rate of a hardware-timed acquisition exceeds the maximum sampling rate of the module, DAQmx generates warning or errors. When a Slow Sample device is in the same task as a non-Slow Sample device, exceeding the maximum sampling rate of the Slow Sample device results in the most recently acquired sample being read multiple times. In this scenario, the first sample of a hardware-timed acquisition with C Series Slow Sample devices is sampled when the task is committed.

    Default Settings for the AI.ADCTimingMode Attribute/Property

    For all modules in the cRIO-9040, 9041, 9042, 9043, 9044, 9045, 9046, 9047, 9048, and 9049 controller, the default value in hardware-timed mode is automatically determined based on Sample Clock Rate.

    Shared Trigger Bus

    On the cRIO-904x controller, NI-DAQmx provides a simple trigger bus between LabVIEW FPGA and NI-DAQmx with the following characteristics:

    • Four fixed direction LabVIEW FPGA to NI-DAQmx Lines:
      • cRIO_Trig0, cRIO_Trig1, cRIO_Trig2, and cRIO_Trig3 are terminals that are driven from LabVIEW FPGA to NI-DAQmx.
      • LabVIEW FPGA: output boolean chassis I/O
      • NI-DAQmx: common-visibility source terminals
        • Can be used with Immediate Routing and Task-Based Routing
        • Does not prescribe to Lazy Line Transitions rules
    • Four Fixed Direction NI-DAQmx to LabVIEW FPGA Lines:
      • cRIO_Trig4, cRIO_Trig5, cRIO_Trig6, and cRIO_Trig7 are terminals that are driven from NI-DAQmx to LabVIEW FPGA.
      • LabVIEW FPGA: input boolean chassis I/O
        • Minimum pulse width requirements:
          • 12.5 ns for most destination terminals
          • 150 ns for SyncPulse terminals
      • NI-DAQmx: common-visibility destination terminals
        • Can be used with Immediate Routing and Task-Based Routing
        • Does not prescribe to Lazy Line Transitions rules
    spd-note-note
    Note  

    The signals available for export from DAQmx vary in pulse width. On a cRIO controller, if you route any of the following signals over the cRIO_Trig bus to the FPGA Target, the pulse is too short to be seen in the default top level clock domain of 40 MHz:

    • Change detection event exported from a buffered change detection DI task
    • Sample clock exported from a hardware-timed digital input or output task running faster than 3.5 MHz
    • Counter output event exported from a counter task that configures its output behavior to pulse

    To fix this problem, consider routing the signal to a counter to widen the pulse.

    NI cRIO Trigger Bus Terminals

    There are two new sets of general-purpose input/output lines for sharing signals between NI-DAQmx tasks and FPGA IO on a NI cRIO chassis.

    • cRIO_Trig0, cRIO_Trig1, cRIO_Trig2, and cRIO_Trig3 are terminals that are driven from the LabVIEW FPGA to NI-DAQmx.
    • cRIO_Trig4, cRIO_Trig5, cRIO_Trig6, and cRIO_Trig7 are terminals that are driven from NI-DAQmx to LabVIEW FPGA.

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