This section contains information on using the cRIO-9040, 9041, 9042, 9043, 9045, 9046, 9047, 9048, 9049, 9053, 9054, 9056, and 9057 controllers with NI-DAQmx.
In MAX, when you add a C Series module to a CompactRIO controller there are three program modes to choose from.
In order for DAQmx to communicate with the module, the module must be in Real-Time (NI-DAQmx) mode.
The cRIO-9040, 9041, 9042, 9043, 9045, 9046, 9047, 9048, 9049, 9053, 9054, 9056, and 9057 controllers support hardware timed single point (HWTSP) sample mode with a few caveats.
CompactRIO may use slightly different C Series model names and product IDs compared to CompactDAQ. For CompactRIO, see C Series Module IDs on ni.com.
cRIO-904x chassis features automatic network-based synchronization with compatible networks and NI Linux RT controllers.
CompactRIO controllers handle sampling rate and the default value for the hardware-timed mode differently than CompactDAQ chassis.
In a cRIO-9040, 9041, 9042, 9043, 9045, 9046, 9047, 9048, 9049, 9053, 9054, 9056, or 9057 controller with C Series Slow Sample devices, such as the NI 9211, if the sampling rate of a hardware-timed acquisition exceeds the maximum sampling rate of the module, DAQmx generates warning or errors. When a Slow Sample device is in the same task as a non-Slow Sample device, exceeding the maximum sampling rate of the Slow Sample device results in the most recently acquired sample being read multiple times. In this scenario, the first sample of a hardware-timed acquisition with C Series Slow Sample devices is sampled when the task is committed.
For all modules in the cRIO-9040, 9041, 9042, 9043, 9045, 9046, 9047, 9048, 9049, 9053, 9054, 9056, and 9057 controllers, the default value in hardware-timed mode is automatically determined based on Sample Clock Rate.
On the cRIO-9040, 9041, 9042, 9043, 9045, 9046, 9047, 9048, 9049, 9053, 9054, 9056, and 9057 controllers, NI-DAQmx provides a simple trigger bus between LabVIEW FPGA and NI-DAQmx with the following characteristics:
The signals available for export from DAQmx vary in pulse width. On a cRIO controller, if you route any of the following signals over the cRIO_Trig bus to the FPGA Target, the pulse is too short to be seen in the default top level clock domain of 40 MHz:
Counter output event exported from a counter task that configures its output behavior to pulse
To fix this problem, consider routing the signal to a counter to widen the pulse.
There are two new sets of general-purpose input/output lines for sharing signals between NI-DAQmx tasks and FPGA IO on a NI cRIO chassis.