NI-DAQmx introduces the concept of a sample timing type. Each sample timing type is a different stimulus for triggering the action of producing a sample. When you select a Timing function/VI, you select your sample timing type. There also is an attribute/property for setting the following sample timing types:
- Sample Clock—A digital edge produces each sample. Nearly all devices have an onboard clock that is dedicated to producing these edges periodically. Even when the edges are not periodic, as they might be when the clock source is something other than the dedicated onboard clock, you still use sample clock timing. Sample clock timing is a type of hardware timing.
- On Demand—Every time the Read or Write function/VI executes, the device produces the requested samples as fast as possible. In this mode, the Sample Quantity attributes/properties are ignored. On-demand timing is a type of software timing.
- Change Detection—Change detection timing captures samples from digital physical channels when NI-DAQmx detects a change-a rising edge, a falling edge, or both rising and falling edges-on one or more digital lines or ports. Change detection timing reduces the digital data an application has to process. One issue to be aware of with change detection on some devices is overflow. Overflow occurs when NI-DAQmx cannot read a sample prior to the next change detection event. The effect is that one or more samples can be missed.
Programmatically, you include the Change Detection Timing function/VI, specifying the physical channels for rising and falling edges on which to detect changes. You can query for an overflow by using the Overflow attribute/property in your application after the task starts.
- Handshake—The handshake sample timing type is used to acquire or generate digital data with the 8255 protocol. Many devices have an 8255 chip, and other devices emulate the 8255 protocol by default with the handshake timing type.
- Burst Handshake—Burst handshake timing acquires or generates digital data on the data lines with a clocked protocol. This timing type involves three control signals: the sample clock, the Pause Trigger, and the Ready for Transfer Event. Data is transferred on each active sample clock edge if the peripheral device deasserts the Pause Trigger and the DAQ device asserts the Ready for Transfer Event.
There are separate Burst Handshake Timing functions/VIs based on whether you import or export a sample clock. Using the appropriate function/VI is important because there are timing restrictions (such as setup and hold times) when sharing a clock between the two devices.
- Implicit—The implicit sample timing type is used for acquiring period or frequency samples using counters. It is also used for generating pulses. This timing type is called implicit because the signal being measured is itself the timing signal or the timing is implicit in the rate of the generated pulse train.