Table Of Contents

SampTimingType

Last Modified: May 21, 2018

Specifies the type of sample timing to use for the task.

Select Sample Clock when a hardware signal (usually a clock) must acquire or produce samples. To perform buffered edge counting, for example, select Sample Clock and use SampClk.Src to specify the source of the Sample clock.

Select Handshake to use bidirectional hardware signals to time the exchange of digital data between two devices.

Select Burst Handshake to run at a slower rate but with the capability for per sample evaluation of triggers and events to pause the operation.

Select Pipelined Sample Clock on supported devices to run at the maximum sample rate with a few Sample clock cycles delay before the device can respond to triggers and events.

Select On Demand to acquire data only when DAQmx Read executes or to generate data only when DAQmx Write executes.

Select Implicit to perform a buffered period or frequency counter measurement or to generate a finite pulse train.

Select Change Detection to capture data only when certain digital lines change states and without continuously transferring unnecessary data during periods of inactivity.

Data type: datatype_icon

Name Value Description
Sample Clock 10388 Acquire or generate samples on the specified edge of the sample clock.
Burst Handshake 12548 Determine sample timing using burst handshaking between the device and a peripheral device.
Handshake 10389 Determine sample timing by using digital handshaking between the device and a peripheral device.
Implicit 10451 Configure only the duration of the task.
On Demand 10390 Acquire or generate a sample on each read or write operation. This timing type is also referred to as static or software-timed.
Change Detection 12504 Acquire samples when a change occurs in the state of one or more digital input lines. The lines must be contained within a digital input channel.
Pipelined Sample Clock 14668 Device acquires or generates samples on each sample clock edge, but does not respond to certain triggers until a few sample clock edges later. Pipelining allows higher data transfer rates at the cost of increased trigger response latency. Refer to the device documentation for information about which triggers pipelining affects. This timing type allows handshaking with some devices using the Pause trigger, the Ready for Transfer event, or the Data Active event. Refer to the device documentation for more information.

Long Name: Timing:Sample Timing Type

Class: DAQmx Task

Permissions: Read/Write

Where This Property Is Available:

Desktop OS: Windows

FPGA:

Web Server: Not supported in VIs that run in a web application


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