Table Of Contents

CO.ConstrainedGenMode

Version:
    Last Modified: May 21, 2018

    Specifies constraints to apply when the counter generates pulses. Constraining the counter reduces the device resources required for counter operation. Constraining the counter can also allow additional analog or counter tasks on the device to run concurrently. For continuous counter tasks, NI-DAQmx consumes no device resources when the counter is constrained. For finite counter tasks, resource use increases with the frequency regardless of the constraint mode. However, fixed frequency constraints significantly reduce resource usage, and fixed duty cycle constraint marginally reduces it.

    Data type: datatype_icon

    Name Value Description
    Unconstrained 14708 Counter has no restrictions on pulse generation.
    Fixed High Frequency 14709 Pulse frequency must be above 7.63 Hz and cannot change while the task runs. In this mode, the duty cycle has 8 bits of resolution.
    Fixed Low Frequency 14710 Pulse frequency must be below 366.21 Hz and cannot change while the task runs. In this mode, the duty cycle has 16 bits of resolution.
    Fixed 50 Percent Duty Cycle 14711 Pulse duty cycle must be 50 percent. The frequency can change while the task runs.

    Long Name: Channel:Counter Output:General Properties:More:Advanced:Constrained Generation Mode

    Class: DAQmx Task

    Permissions: Read/Write

    Where This Property Is Available:

    Desktop OS: Windows

    FPGA:

    Web Server: Not supported in VIs that run in a web application


    Recently Viewed Topics