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AI.ADCTimingMode

Version:
    Last Modified: May 21, 2018

    Specifies the ADC timing mode, controlling the tradeoff between speed and effective resolution. Some ADC timing modes provide increased powerline noise rejection. On devices that have an AI Convert clock, this setting affects both the maximum and default values for AIConv.Rate. You must use the same ADC timing mode for all channels on a device, but you can use different ADC timing modes for different devices in the same task.

    Data type: datatype_icon

    Name Value Description
    High Resolution 10195 Increases resolution and noise rejection while decreasing conversion rate.
    High Speed 14712 Increases conversion rate while decreasing resolution.
    Best 50 Hz Rejection 14713 Improves 50 Hz noise rejection while decreasing noise rejection at other frequencies.
    Best 60 Hz Rejection 14714 Improves 60 Hz noise rejection while decreasing noise rejection at other frequencies.
    Custom 10137 Use AI.ADCCustomTimingMode to specify a custom value controlling the tradeoff between speed and resolution.

    Long Name: Channel:Analog Input:General Properties:Digitizer/ADC:Timing Mode

    Class: DAQmx Task

    Permissions: Read/Write

    Where This Property Is Available:

    Desktop OS: Windows

    FPGA:

    Web Server: Not supported in VIs that run in a web application


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