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Lead Lag (G Dataflow)

Version:
Last Modified: August 28, 2017

Implements a PID controller with a lead or lag function, which is generally used as a dynamic compensator in feedforward control schemes.

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reset

A Boolean or a Boolean array that specifies the initialization of the internal state of the node.

True Initializes the output to the current input value.
False Does not initialize the output to the current input value.

Default: False

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input

Input signal.

This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.

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tuning parameters

Tuning parameters to adjust the controller.

This input accepts a cluster or an array of clusters.

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gain

DC gain. Setting gain to a negative value produces an inverting amplifier with an additional 180-degree phase shift.

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lag time

Phase lag in seconds. A value of zero turns off the lag.

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lead time

Phase lead in seconds. A value of zero turns off the lead. Large lead time values might result in a wild oscillation of the output.

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dt

Loop-cycle time or interval, in seconds, at which this node is called.

dt must be greater than zero.

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output

Control output of the PID algorithm that is applied to the controlled process.

This output can return a double-precision, floating-point number or an array of double-precision, floating-point numbers.

Where This Node Can Run:

Desktop OS: Windows

FPGA: This product does not support FPGA devices

Web Server: Not supported in VIs that run in a web application


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