Executes each iteration of its subdiagram at the period you specify.
Use the Timed Loop when you want to develop programs with multirate timing capabilities, precise timing, feedback on loop execution, or several levels of execution priority.
Defines the system settings for the Timed Loop, such as the processor that handles execution of the loop and the priority of the execution of the loop.
Generates execution timing information for each iteration.
Defines and returns the timing settings for the Timed Loop, such as the loop period and the timing source that controls the loop.
Propagates errors through the loop. The Timed Loop does not execute if this border node receives an error condition.
Propagates errors or warnings out of the loop subdiagram. If this border node receives an error condition, the Timed Loop finishes executing the current iteration untimed, exits the loop, and returns the error condition.
Current loop iteration count. The loop count always starts at zero for the first iteration. The maximum number of iterations is 2,147,483,647, or 231-1.
If you need to keep count of more than 2,147,483,647 iterations, you can use shift registers with a greater integer range.
Determines whether to continue executing the loop. The loop runs infinitely by default. To specify whether the loop stops for a TRUE or FALSE Boolean value, configure the continuation behavior.
Point through which data enters or exits a structure.
You can configure a conditional output for any tunnel type by selecting the tunnel and clicking the Conditional checkbox in the Item tab. When the conditional input for a tunnel is True, the loop writes the corresponding value to the tunnel. When the condition input for the tunnel is False, the loop doesn't write the corresponding value to the tunnel.
Member of a pair of terminals that passes a value from one iteration of a loop to the next iteration. After the initial loop iteration, the left shift register in the pair returns the value it receives from the right shift register from the previous iteration.
Refer to Accessing Data from the Previous Loop Iteration for more information about passing values from the previous iteration to the current iteration.
A Timed Loop might execute later than the time you specify. For example, higher priority Timed Loops may monopolize processor resources and prevent timely execution of a lower priority Timed Loop. You must configure mode in on the Timing Source node on a Timed Loop to handle late execution.
Use the following table to compare the mode in options of the Timed Loop.
|mode in Option||Effect on Schedule||Effect on Data Processing|
|1 – Process missed periods, maintain original phase||Realigns with the original schedule.||Processes data that became available during missed iterations.|
|2 – Discard missed periods, maintain original phase||Realigns with the original schedule.||Discards data that became available during missed iterations.|
|3 – Process missed periods, ignore original phase||Enables definition of a new schedule that starts at the current time.||Processes data that became available during missed iterations.|
|4 – Discard missed periods, ignore original phase||Enables definition of a new schedule that starts at the current time.||Discards data that became available during missed iterations.|
As the table describes, each mode configuration option affects two settings of the Timed Loop:
Whether execution of the Timed Loop aligns with the original schedule or enables definition of a new schedule.
For example, if you set a Timed Loop with a period of 100 ms and an offset of 30 ms, you expect the first loop iteration to execute 30 ms after the first timing source starts running and in multiples of 100 ms after that—at 130 ms, 230 ms, 330 ms, and so on. However, the first execution of the Timed Loop might occur after 240 ms have elapsed. If other Timed Loops or hardware devices are already running at the schedule you specified, you can select option 1 or 2 to configure the Timed Loop to align itself as quickly as possible with the schedule you specified. With this setting, the next Timed Loop iteration will run at 330 ms and continue to run in multiples of 100—at 430 ms, 530 ms, and so on.
If aligning the Timed Loop with other Timed Loops or other hardware devices is not important, select option 3 or 4 to configure the Timed Loop to run immediately and use the current time as its actual offset. With this setting, the subsequent loop iterations run at 240 ms, 340 ms, 440 ms, and so on.
Whether the Timed Loop processes or discards data that becomes available during missed iterations.
If the Timed Loop is late, it might miss data that other Timed Loops or hardware devices generate. For example, if the Timed Loop misses two iterations and some of the data from the current period, a buffer can hold the data from the missed iterations. Select option 1 or 3 to configure the Timed Loop to process the missed data before it aligns with the schedule. Be aware that processing missed data causes jitter, or a variance between the loop cycle time and the time you specified. To avoid jitter, select option 2 or 4 to configure the Timed Loop to discard older data and process only the latest available data in the buffer.
The Timed Loop is a deterministic structure, which means that all Timed Loops execute before any other code on the diagram.
Because of the preemptive nature of Timed Loops, they can monopolize processor resources, not allowing other tasks on the diagram to execute. You must configure the highest priority Timed Loop with a period that is large enough to execute the code on the Timed Loop subdiagram and also have enough idle time during every iteration to allow the rest of the code on the diagram to execute.
Where This Node Can Run:
Desktop OS: Windows
FPGA: This product does not support FPGA devices
Web Server: Not supported in VIs that run in a web application