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fir_win

Version:
    Last Modified: March 15, 2017

    Uses the window design method to design a linear phase FIR filter. This function windows the impulse response with a Hamming window by default.

    Syntax

    b = fir_win(n, w)
    b = fir_win(n, w, option)
    b = fir_win(n, w, window)
    b = fir_win(n, w, s)
    b = fir_win(n, w, option, window)
    b = fir_win(n, w, option, s)
    b = fir_win(n, w, option, window, s)
    Legacy name: fir1

    Inputs

    n

    Filter order. n is a nonnegative integer. n must be even for filters with a non-zero gain at the Nyquist frequency. If n does not meet this condition, MathScript increases n by 1.

    w

    Cutoff frequencies of the filter. w is real scalar or ascending vector with elements between 0 and 1. 1 represents the Nyquist frequency. fir_win generally designs a multiband FIR filter with bands 0<w<w 1, w 1<w<w 2w n<w<1.

    option

    Type of filter to design. option is a string that accepts the following values:

    Name Description
    'low'

    Lowpass filter.

    'high'

    Highpass filter.

    'bandpass'

    Bandpass filter.

    'stop'

    Stopband filter.

    'DC-0'

    Multiband filter whose first band is a stopband.

    'DC-1'

    Multiband filter whose first band is a passband.

    Default: 'low'

    window

    Window coefficients. The length of window must equal n + 1. If n is even and the filter has a non-zero gain at the Nyquist frequency, the length of window must equal n + 2.

    s

    Specifies whether the magnitude of the designed filter is normalized. s is a string that accepts the following values:

    Name Description
    'scale'

    Directs MathScript to scale the filter coefficients.

    'noscale'

    Directs MathScript not to scale the filter coefficients.

    Default: 'scale'

    Outputs

    b

    Filter coefficients of order n. b is a real vector.

    N = 5;
    W = 0.2;
    B = fir_win(N, W, 'low', win_hann2(6))

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: This product does not support FPGA devices


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