Table Of Contents

Upsample (G Dataflow)

Version:
    Last Modified: March 15, 2017

    Inserts zeros in a sequence according to a specific upsampling factor.

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    signal

    A real vector.

    This input accepts the following data types:

    • Waveform
    • Waveform in complex double-precision, floating-point numbers
    • 1D array of waveforms
    • 1D array of waveforms in complex double-precision, floating-point numbers
    • 1D array of double-precision, floating-point numbers
    • 2D array of double-precision, floating-point numbers
    • 1D array of complex double-precision, floating-point numbers
    • 2D array of complex double-precision, floating-point numbers
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    upsampling factor

    Number of zeros between two adjacent samples.

    This node inserts upsampling factor - 1 zeros into every two elements in signal. upsampling factor must be greater than zero.

    Default: 1

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    leading zeros

    Number of leading zeros in the output upsampled sequence.

    leading zeros must be greater than or equal to zero and less than upsampling factor.

    Default: 0

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    error in

    Error conditions that occur before this node runs.

    The node responds to this input according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Default: No error

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    upsampled signal

    Upsampled sequence.

    The length of upsampled signal is the upsampling factor times the length of signal.

    This output can return the following data types:

    • Waveform
    • Waveform in complex double-precision, floating-point numbers
    • 1D array of waveforms
    • 1D array of waveforms in complex double-precision, floating-point numbers
    • 1D array of double-precision, floating-point numbers
    • 2D array of double-precision, floating-point numbers
    • 1D array of complex double-precision, floating-point numbers
    • 2D array of complex double-precision, floating-point numbers
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    error out

    Error information.

    The node produces this output according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Algorithm for Upsampling

    If Y represents the output sequence upsampled signal, this node obtains the elements of the sequence Y using the following equation:

    Y i = { x j if i = j * m + k 0 otherwise

    for i = 0, 1, 2, ..., size - 1,

    size = n * m,

    where

    • n is the number of elements in signal
    • m is the upsampling factor
    • k is leading zeros
    • size is the number of elements in the output sequence upsampled signal

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: This product does not support FPGA devices


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