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Schur Decomposition (G Dataflow)

Version:
    Last Modified: March 15, 2017

    Performs the Schur decomposition of a square matrix.

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    matrix A

    A square real matrix.

    This input accepts a 2D array of double-precision, floating point numbers or 2D array of complex double-precision, floating point numbers.

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    compute Schur vectors?

    A Boolean that determines whether this node calculates the orthogonal matrix.

    True Calculates the orthogonal matrix and the block upper triangular matrix in real Schur form.
    False Calculates only the block upper triangular matrix in real Schur form.

    Default: False

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    order

    Method to order the eigenvalues and the corresponding triangular matrix in real Schur form and the orthogonal matrix.

    Name Value Description
    No Reorder 0 Does not change the order of the eigenvalues.
    Real Ascending 1 Lists the eigenvalues in ascending order according to their real parts.
    Real Descending 2 Lists the eigenvalues in descending order according to their real parts.
    Magnitude Ascending 3 Lists the eigenvalues in ascending order according to their magnitudes.
    Magnitude Descending 4 Lists the eigenvalues in descending order according to their magnitudes.

    Default: No Reorder

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    error in

    Error conditions that occur before this node runs.

    The node responds to this input according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Default: No error

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    Schur form

    The block upper triangular matrix in real Schur form.

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    Schur vectors

    The orthogonal matrix.

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    eigenvalues

    A complex vector that contains all the computed eigenvalues of the input matrix.

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    error out

    Error information.

    The node produces this output according to standard error behavior.

    Standard Error Behavior

    Many nodes provide an error in input and an error out output so that the node can respond to and communicate errors that occur while code is running. The value of error in specifies whether an error occurred before the node runs. Most nodes respond to values of error in in a standard, predictable way.

    error in does not contain an error error in contains an error
    If no error occurred before the node runs, the node begins execution normally.

    If no error occurs while the node runs, it returns no error. If an error does occur while the node runs, it returns that error information as error out.

    If an error occurred before the node runs, the node does not execute. Instead, it returns the error in value as error out.

    Algorithm for Calculating Schur Decomposition

    The following expression defines the Schur decomposition of a square n × n matrix A.

    A = QSQH

    where S is in Schur form and QH is the conjugate transpose of matrix Q.

    For a real matrix A, Q is an n × n orthogonal matrix. S is a block upper triangular matrix in real Schur form, whose elements on the main diagonal are all 1 × 1 or 2 × 2 blocks, as shown in the following matrix.

    S = [ S 11 S 12 S 1 m 0 S 22 S 2 m 0 0 S m m ]

    where Sii are square blocks of dimension 1 or 2 and i = 1, 2, ..., m.

    For a complex matrix A, Q is an n × n unitary matrix. S is an upper triangular matrix in complex Schur form.

    Where This Node Can Run:

    Desktop OS: Windows

    FPGA: This product does not support FPGA devices


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