From 6:00 PM CST Friday, Feb 15th - 2:00 AM CST Sunday, Feb 17th, ni.com will be undergoing system upgrades that may result in temporary service interruption.

We appreciate your patience as we improve our online experience.

Table Of Contents

Quantizer (G Dataflow)

Last Modified: March 31, 2017

Quantizes a continuous input signal to discrete states.

connector_pane_image
datatype_icon

input

Input signal.

This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.

datatype_icon

quantization interval

Height of the quantization levels.

This input accepts a double-precision, floating-point number or an array of double-precision, floating-point numbers.

Default: 1

datatype_icon

type of quantization

Type of the quantizer.

This input accepts a ring or an array of rings.

Name Value Description
Mid-tread 0 Uses a mid-tread type quantizer.
Mid-riser 1 Uses a mid-riser type quantizer.
Round towards +Inf 2 Rounds the input elements to the nearest integer towards +Inf.
Round towards -Inf 3 Rounds the input elements to the nearest integer towards -Inf.
Round towards zero 4 Rounds the input elements to the nearest integer towards zero.
Round away from zero 5 Rounds the input elements to the nearest integer away from zero.

Algorithm Definition for the Mid-Tread Quantizer

The mid-tread quantizer uses the following equation to quantize the input signal.

y = [ u Δ ] * Δ

where

  • y is the output signal
  • u is the input signal
  • Δ is the quantization interval

Algorithm Definition for the Mid-Riser Quantizer

The mid-riser quantizer uses the following equation to quantize the input signal.

y = u Δ 0.5 * Δ

where

  • y is the output signal
  • u is the input signal
  • Δ is the quantization interval

Default: Mid-tread

datatype_icon

output

Output signal.

This output can return a double-precision, floating-point number or an array of double-precision, floating-point numbers.

Where This Node Can Run:

Desktop OS: Windows

FPGA: This product does not support FPGA devices


Recently Viewed Topics