Generates a signal containing a chirp pattern.
Amplitude of the pattern.
Beginning frequency of the pattern in normalized units of cycles/sample.
Ending frequency of the pattern in normalized units of cycles/sample.
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: No error
Number of samples in the signal.
Output chirp pattern. The output pattern contains frequency ramping from f1*fs to f2*fs, where fs is the sampling rate.
Error information. The node produces this output according to standard error behavior.
If the sequence Y represents chirp pattern, this node obtains the elements of Y using the following equation:
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported