Creates a 1MHz timing source you can use to control the execution of a timed structure. Each timing source does not start until the first timed structure that uses the timing source starts.
The name of the timing source you want to create.
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: No error
The name of the timing source created by the node.
Error information. The node produces this output according to standard error behavior.
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported