Last Modified: January 9, 2017

Simulates the operation of the phase-locked loop (PLL) in response to an input real passband waveform that has an unknown phase and frequency offset.

This node attempts to track the unknown phase of an input complex exponential tone by means of a feedback control system. At steady state, when the PLL has acquired a lock to the input signal, the PLL estimates the offset of the input signal carrier phase and carrier frequency from the reference phase and frequency. The passband waveform is assumed to consist of a tone at a user-specified nominal carrier phase and frequency, which is used as a reference to the PLL. The PLL is a feedback control system that employs a phase detector, loop filter, and a voltage-controlled oscillator (VCO) for its operation. The PLL tracks the instantaneous phase and frequency of the input waveform and returns an estimate of the carrier phase and frequency. You can use these estimates to adjust or correct the phase of the input waveform (for example, carrier phase or frequency offset correction in M-ary PSK digital communication systems).

A passband waveform comprising of a tone at the carrier, with a frequency and phase that are to be estimated by the PLL.

The reference carrier frequency, in Hertz (Hz), which is used by the VCO to track the carrier phase of the input signal.

**Default: **0

The reference initial carrier phase, in degrees, which is used by the VCO to track the carrier phase of the input signal.

**Default: **0

The gain applied to the error signal inside the VCO before generating the **estimated initial phase** parameter.

**Default: **1

Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.

**Default: **no error

The forward coefficients of the IIR loop filter.

**Default: **(1.05 -0.95)

A Boolean that determines whether to clear the internal state of the PLL prior to starting operation.

TRUE | Clears all state information, and initializes the PLL with the initial phase given in the PLL settings cluster. |

FALSE | Uses the state information at the end of the previous iteration to initialize the PLL at the beginning of the current iteration. |

**Default: **TRUE

The reverse coefficients of the IIR loop filter.

**Default: **(1 -1)

The overall phase of the input signal estimated by the PLL, including the effects of any carrier phase and frequency offsets.

The carrier phase error signal at the phase detector output inside the PLL. You can use this value to estimate the phase difference between the input signal and the regenerated phase at the PLL output. When the PLL locks, **phase error** values approach zero.

The actual carrier frequency of the input signal, as estimated by the PLL, accounting for any carrier frequency offset. Use the difference between the estimated carrier frequency and the nominal input carrier frequency to estimate the carrier frequency offset.

The actual carrier phase of the input signal, as estimated by the PLL, with respect to the specified nominal carrier phase. Use the difference between the estimated carrier phase and the input nominal carrier phase to estimate the scalar carrier phase offset.

The PLL nodes are continuable, meaning that you can successively send a phase-continuous signal to the node over multiple iterations when **reset?** is set to FALSE. A PLL contains three basic elements:

The phase detector block measures the approximate error between the estimated phase and the actual phase of the incoming signal. The IIR loop filter block then filters out any high-frequency noise present in the error signal and helps tracking phase and frequency offset errors. A first-order lowpass filter block tracks an initial phase offset, but returns a constant phase offset in the presence of a frequency offset. Higher-order filters track both phase and frequency offsets at steady state, as summarized in the following table.

F(s) | F(z) | Comments |
---|---|---|

1 | 1 | (Order I) Tracks frequency error, steady state phase offset |

$1+\frac{a}{s}$ | $\frac{(0.5a+1)+(0.5a-1){z}^{-2}}{1-{z}^{-1}}$ | (Order II) Tracks phase and frequency error, not offset |

$\frac{s+a}{s+\epsilon}$ | $M\frac{1-\left(\frac{2-a}{2+a}\right){z}^{-1}}{1-\left(\frac{2-\epsilon}{2+\epsilon}\right){z}^{-1}}$ | (Order II) Tracks phase and frequency error, not offset |

$1+\frac{a}{s}+\frac{b}{{s}^{2}}$ | $\frac{(4+2a+b)+(2b-8){z}^{-1}+(b-2a+4){z}^{-2}}{4(1-2{z}^{-1}+{z}^{-2})}$ | (Order III) Tracks phase and frequency error, not offset |

**Where This Node Can Run: **

Desktop OS: Windows

FPGA: Not supported