Performs the interleaving process with delays that you specify for each branch.
Each branch has different delays associated with it. Hence, the data input of each interleaver branch is delayed by a specific amount (the amount of delay in that branch) before the interleaver returns the data. A convolutional interleaver is twice as efficient as a block interleaver.
The input data to the interleaver.
The number of delays individually for each branch of the corresponding interleaver. The number of elements in this array determines the number of branches, and the value of each element denotes the delay for that branch. For example, if interleaver delays is [3,6,9,2], it implies that there are four branches; branch 0 has 3 delays, branch 1 has 6 delays, and so on.
The shift register values when the convolutional interleaver begins operation.
Error conditions that occur before this node runs. The node responds to this input according to standard error behavior.
Default: no error
The convolutional interleaved data returned by this node.
Error information. The node produces this output according to standard error behavior.
The following example demonstrates convolutional interleaving and deinterleaving. Let the data in be: x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, x10, x11, x12, x13, …
D = unit delay in the path.
Assume for this example that the unit delay = 1, and the initial state shift registers are initialized with values of 0 for both the interleaver and the deinterleaver.
Interleaved Data: x0, 0, 0, 0, x4, x1, 0, 0, x8, x5, x2, 0, x12, x9, …
Deinterleaved Data: 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, x0, x1, x2, x3, x4, x5, x6, x7, x8, x9, …
Where This Node Can Run:
Desktop OS: Windows
FPGA: Not supported