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Restrictions for Calling a Multirate Diagram

Last Modified: February 16, 2016

You can call a Multirate diagram only in specific circumstances.

Consider the following restrictions when calling a Multirate diagram:

  • You can call a Multirate diagram only from a VI targeted to a host or FPGA.
  • If you call a Multirate diagram from a VI targeted to an FPGA, the Multirate Diagram node must be outside of a Clock-Driven Loop.
  • You cannot call a Multirate diagram from an Optimized FPGA VI, from a Clock-Driven Logic document, or from the inside of a Clock-Driven Loop.

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